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Freescale Semiconductor Technical Data
MMA52xxWR2 Rev 0, 02/2010
PSI5 Inertial Sensor
The MMA52wwWR2 family of devices are AKLV27 and PSI5 Version 1.3 compatible overdamped X-axis satellite accelerometers. Features 60g to 480g Full-Scale Range Selectable 400 Hz, 3 Pole, or 4 pole Low Pass Filter Single Pole High Pass Filter with Fast Start-Up & Output Rate Limiting PSI5 Version 1.3 Compatible - PSI5-P10P-500/3L Compatible - Programmable Time Slots with 0.5 s Resolution - Selectable Baud Rate: 125 kBaud or 190.5 kBaud - Selectable Data Length: 8 or 10 bits - Selectable Error Detection: Even Parity, or 3-bit CRC - Optional Daisy Chain with External Low Side Switch - Two-Wire Programming Mode * 16 s Internal Sample Rate, with Interpolation to 1 s * Pb-Free 16-Pin QFN, 6 x 6 Package * Qualified AECQ100, Revision G, Grade 1 (-40C to +125C) Typical Applications * Airbag Front and Side Crash Detection
VSSA
MMA52xxWR2
* * * *
PSI5 INERTIAL SENSOR
Bottom View
16-PIN QFN CASE 2089-01
Top View
BUS_SW
TEST
16 15 14 13
ORDERING INFORMATION
Device MMA5206W MMA5206WR2 MMA5206KW MMA5206KWR2 MMA5212W MMA5212WR2 MMA5212KW MMA5212KWR2 MMA5224W MMA5224WR2 MMA5224KW MMA5224KWR2 MMA5248W MMA5248WR2 MMA5248KW MMA5248KWR2 Axis X X X X X X X X X X X X X X X X Temperature Range 60g 60g 60g 60g 120g 120g 120g 120g 240g 240g 240g 240g 480g 480g 480g 480g Package 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 2089-01 Shipping Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel
VCC 1 VSS 2 IDATA 3 VSS 4
VBUF 12 VSSA 11 VREGA 10 CS 9 VREG 8 DIN
17
5 PCM
6 SLCK
7 DOUT
PIN CONNECTIONS
"K" suffix indicates device manufactured with an alternate silicon sourcing.
This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2010. All rights reserved.
VVBUF VBUF VREG VREGA
C4 C5 C6
VCC IDATA
R1 R2 C2 C3 C1
VCE
MMA52xx
VSSA VSS
R3
CS SCLK DO
VSS
Note: Pin names and references may differ from PSI5 V1.3 pin names and references
DI PCM
BUS_SW Optional for Daisy Chain
M1
VSS_OUT
Figure 1. Application Diagram
External Component Recommendations Ref Des
C1 C3 C2 C4, C5, C6 R1 R2 R3 M1
Type
Ceramic Ceramic Ceramic Ceramic General Purpose General Purpose General Purpose N-Channel MOSFET
Description
2.2 nF, 10%, 50 V minimum, X7R 470 pF, 10%, 50 V minimum, X7R 15 nF, 10%, 50 V minimum, X7R 1 mF, 10%, 10 V minimum, X7R 82 , 5%, 200 PPM 27 , 5%, 200 PPM 20 k, 5%, 200 PPM --
Purpose
VCC Power Supply Decoupling and Signal Damping IDATA Filtering and Signal Damping VCC Power Supply Decoupling Voltage Regulator Output Capacitor(s) VCC Filtering and Signal Damping IDATA Filtering and Signal Damping Gate Resistor for External Low Side Daisy Chain FET Low Side Daisy Chain Transistor
Device Orientation
xxxxxxx xxxxxxx
X: 0 g
MMA52xxWR Preliminary 2 Sensors Freescale Semiconductor
xxxxxxx xxxxxxx X: +1 g
Figure 2. Device Orientation Diagram
xxxxxxx xxxxxxx X: 0 g
xxxxxxx xxxxxxx X: -1 g X: 0 g X: 0 g
EARTH GROUND
Internal Block Diagram
VCC
Buffer Voltage Regulator Reference Voltage
VBUF
Digital Voltage Regulator Analog Voltage Regulator
VBUF VREG VREG
VREF
VREGA VBUF
VREGA VSSA
CS SCLK DIN DOUT
Control Logic
SPI
Low Voltage Detection Sync Pulse Detection Programming Interface
VCC
OTP Array
IDATA Serial Encoder VSS Daisy Chain Switch Driver BUS_SW
VREG
Self-Test Interface Control In Status Out DSP Converter
VREGA g-cell
VREG
Offset Monitor HPF PCM Encoder PCM
SINC Filter
IIR LPF
Compensation
Figure 3. Block Diagram
MMA52xxWR Sensors Freescale Semiconductor Preliminary 3
1
PIN CONNECTIONS
BUS_SW TEST VBUF 12 VSSA 11 VREGA 10 CS 9 VREG 5 PCM 6 SLCK 7 DOUT 8 DIN
Definition
This pin is connected to the PSI5 power and data line through a resistor and supplies power to the device. An external capacitor must be connected between this pin and VSS. Reference Figure 1. This pin is the power supply return node for the digital circuitry. This pin is connected to the PSI5 power and data line through a resistor and modulates the response current for PSI5 communication. Reference Figure 1. This pin is the power supply return node for the digital circuitry. This pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. The output can be enabled via OTP. Reference Section 3.5.3.7. If unused, this pin must be left unconnected. This input pin provides the serial clock to the SPI port for test purposes. An internal pull-down device is connected to this pin. This pin must be grounded or left unconnected in the application. This pin functions as the serial data output from the SPI port for test purposes. This pin must be left unconnected in the application. This pin functions as the serial data input to the SPI port for test purposes. An internal pull-down device is connected to this pin. This pin must be grounded or left unconnected in the application. This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1. This input pin provides the chip select to the SPI port for test purposes. An internal pull-up device is connected to this pin.This pin must be left unconnected in the application. This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1. This pin is the power supply return node for the analog circuitry. This pin is connected to a buffer regulator for the internal circuitry. The buffer regulator supplies both the analog (VREGA) and digital (VREG) supplies to provide immunity from EMC and supply dropouts on VCC. An external capacitor must be connected between this pin and VSS. Reference Figure 1. This pin is must be grounded or left unconnected in the application. This pin is the drive for a low side daisy chain switch. When daisy chain mode is enabled, this pin is connected to the gate of an n-channel FET which connects VSS to VSS_OUT. Reference Figure 1. If unused, this pin must be left unconnected. This pin is the power supply return node for the analog circuitry. This pin is the die attach flag, and is internally connected to VSS. Reference Section 7 for die attach pad connection details.
16 15 14 13 VCC 1 VSS 2 IDATA 3 VSS 4 17
Figure 4. Top View, 16-Pin QFN Package Table 1. Pin Description
Pin
1 2 3 4 5
Pin Name
VCC VSS IDATA VSS PCM
Formal Name
Supply Digital GND Response Current Digital GND PCM Output SPI Clock
6
SCLK
7
DOUT
SPI Data Out
8
DIN
SPI Data In Digital Supply Chip Select Analog Supply Analog GND Power Supply Test Pin Bus Switch Gate Drive Analog GND Die Attach Pad
9
VREG CS
10
11 12
VREGA VSSA
13
VBUF TEST BUS_SW VSSA PAD
14 15 16 17
MMA52xxWR Preliminary 4 Sensors Freescale Semiconductor
VSSA
2
2.1
#
1 2 3 4 5 6 7 8
ELECTRICAL CHARACTERISTICS
Maximum Ratings
Rating
Supply Voltage (VCC, IDATA) Reverse Current 160 mA, t 80 ms Continuous Transient (< 10 s) VBUF, Test, BUS_SW VREG, VREGA, SCLK, CS, DIN, DOUT, PCM Powered Shock (six sides, 0.5 ms duration) Unpowered Shock (six sides, 0.5 ms duration) Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation) Electrostatic Discharge (per AEC-Q100) External Pins (VCC, IDATA, VSS, VSSA), HBM (100 pF, 1.5 k) HBM (100 pF, 1.5 k) CDM (R = 0 ) MM (200 pF, 0 ) Temperature Range Storage Junction Thermal Resistance gpms gshock hDROP VESD VESD VESD VESD Tstg TJ JC
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.
Symbol
VCC_REV VCC_MAX VCC_TRANS
Value
-0.7 +20.0 +25.0 -0.3 to +4.2 -0.3 to +3.0 2000 2500 1.2 4000 2000 1500 200 -40 to +125 -40 to +150 2.5
Unit
V V V V V g g m (3) (3) (9) (3) (3) (3) (3) (5)
9 10 11 12
V V V V
(5) (5) (5) (5)
13 14 15
C C C/W
(3) (9) (9,14)
2.2
#
16 17 18
Operating Range
Characteristic
Supply Voltage Programming Voltage (IDATA 85 mA) Applied to IDATA, VCC Operating Temperature Range
VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified
Symbol
VCC VCC_UV VPP
Min
VL 4.2 VVCC_UV_F 14.0 TL -40
Typ
-- --
Max
VH 17.0 VL -- TH +125
Units
V V (1) (9)
--
V
(3)
19
TA
--
C
(1)
MMA52xxWR Sensors Freescale Semiconductor Preliminary 5
2.3
#
20 21 22
Electrical Characteristics - Supply and I/O
Characteristic
Quiescent Supply Current Modulation Supply Current Inrush Current (Power On until VBUF, VREG, VREGA Stable) Internally Regulated Voltages VBUF VREG VREGA Low Voltage Detection Threshold VCC Falling VBUF Falling VREG Falling VREGA Falling Hysteresis VCC VBUF VREG VREGA External Capacitor (VBUF, VREG, VREGA ) Capacitance ESR (including interconnect resistance) Synchronization Pulse (Figure 5) VIDLE Voltage Range DC Sync Pulse Detection Threshold Sync Pulse Pull-down Current Output High Voltage (DO) ILoad = 100 A Output Low Voltage (DO) ILoad = 100 A Input High Voltage CS, SCLK, DI Input Low Voltage CS, SCLK, DI Input Current High (at VIH) (SCLK, DI) Low (at VIL) (CS) Pull-down Resistance (SCLK) Temperature Monitoring Under-Temperature Monitor Threshold Over-Temperature Monitor Threshold BUS_SW Output High Voltage (BUS_SW) ILoad = 100 A Output Low Voltage (BUS_SW) ILoad = 100 A Daisy Chain Addressing Mode Sync Pulse Period Bus Switch Output Activation Time (C = 50 pF) From last bit of "SetAdr" Response to 80% of VBUS_SW_OH Sync Pulse Blanking Time after "SetAdr" Command Received From last bit of "SetAdr" Response * *
VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified.
Symbol IIDLE IMOD IINRUSH Min 4.0 IIDLE+ 22.0 -- Typ -- IIDLE+ 26.0 -- Max 8.0 IIDLE+ 30.0 30 Units mA mA mA (1) (1) (3)
23 24 25 26 27 28 29
* * *
VBUF VREG VREGA
3.60 2.425 2.425
3.80 2.50 2.50
4.00 2.575 2.575
V V V
(1) (1) (1)
VVCC_UV_F VBUF_UV_F VREG_UV_F VREGA_UV_F VCC_HYST VBUF_HYST VREG_HYST VREGA_HYST
3.40 2.95 2.15 2.15 0.10 0.05 0.05 0.05
3.70 3.15 2.25 2.25 0.25 0.10 0.10 0.10
4.0 3.35 2.35 2.35 0.40 0.15 0.15 0.15
V V V V V V V V
(3,6) (3,6) (3,6) (3,6) (3) (3) (3) (3)
30 31 32 33
34 35
ESR
500 0
1000 --
1500 200
nF m
(9) (9)
36 37 38
* *
VIDLE VSYNC ISYNC_PD
-- VIDLE+1.4 --
-- VIDLE+2.0 IMOD - IIDLE
15.4 VIDLE+2.6 --
V V mA
(3,11) (3,6) (3)
39
VOH
VREG - 0.1
--
--
V
(9)
40
VOL
--
--
0.1
V
(9)
41
VIH
0.7 * VREG
--
--
V
(9)
42
VIL
--
--
0.3 * VREG
V
(9)
43 44 45
IIH IIL
-100 10
-- --
-10 100
A A
(9) (9)
RPD TIH TIL VBUS_SW_OH VBUS_SW_OL
20
ae
100
kW
(9)
46 47
-- 155
-- --
-55 --
C C
(9) (9)
48
3.15
--
VBUF 0.45 --
V
(9)
49 50
0.0 --
-- tS-S_PM_L -- 200000 / fOSC
V s s s
(9) (7)
51
tBUS_SW tDC_BLANKING
--
300
(7) (7)
52
MMA52xxWR Preliminary 6 Sensors Freescale Semiconductor
2.4
#
53 54 55 56 57 58 59 60 61 62
Electrical Characteristics - Sensor And Signal Chain
Characteristic
Sensitivity (10-bit output @ 100 Hz, referenced to 0 Hz) 60g Range 120g Range 240g Range 480g Range Total Sensitivity Error (including non-linearity) TA = 25C, 240g TL TA TH, 240g TL TA TH, 240g, VVCC_UV_F VCC VL TA = 25C, > 240g TL TA TH, > 240g TL TA TH, > 240g, VVCC_UV_F VCC VL Digital Offset Before Offset Cancellation 10-bit 10-bit, TL TA TH, VVCC_UV_F VCC VL Digital Offset After Offset Cancellation 10-bit, 0.3 Hz HPF or 0.1 Hz HPF 10-bit, 0.04 Hz HPF Continuous Offset Monitor Limit 10-bit output, before compensation Range of Output (10-bit Mode) Acceleration Cross-Axis Sensitivity Z-axis to X-axis Y-axis to X-axis System Output Noise Peak (10-bit Mode, 1 Hz - 1 kHz, All Ranges) System Output Noise RMS (10-bit mode, 1 Hz - 1 kHz, All Ranges) Non-linearity 10-bit output, 240g 10-bit output, > 240g * * * * * * * *
VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified.
Symbol
SENS SENS SENS SENS SENS_240 SENS_240 SENS_240 SENS_480 SENS_480 SENS_480
Min
-- -- -- -- -5 -7 -7 -5 -7 -7
Typ
0.1250 0.2500 0.5000 1.0000 -- -- -- -- -- --
Max
-- -- -- -- +5 +7 +7 +5 +7 +7
Units
g/LSB g/LSB g/LSB g/LSB % % % % % % (1) (1) (1) (1) (1) (1) (9) (1) (1) (9)
63 64
*
OFF10Bit OFF10Bit OFF10Bit OFF10Bit OFFMON RANGE
-52 -52
0 0
+52 +52
LSB LSB
(1) (9)
65 66
* *
-1 -2
0 0
+1 +2
LSB LSB
(1) (9)
67
-66
--
+66
LSB
(3)
68
-480
--
+480
LSB
(3)
69 70 71 72
* * * *
VZX VYX nPeak nRMS NLOUT_240g NLOUT_480g
-5 -5 -4 --
-- -- -- --
+5 +5 +4 +1.0
% % LSB LSB
(3) (3) (3) (3)
73 74
-2 -2
-- --
+2 +2
% %
(3) (3)
2.5
#
75 76 77 78
Electrical Characteristics - Self-Test and Overload
Characteristic
10-Bit Output During Active Self-Test (TL TA TH) 60g Range 120g Range 240g Range 480g Range Acceleration (without hitting internal g-cell stops) 60g Range Positive/Negative Acceleration (without hitting internal g-cell stops) 120g Range Positive/Negative Acceleration (without hitting internal g-cell stops) 240g Range Positive/Negative Acceleration (without hitting internal g-cell stops) 480g Range Positive/Negative and Sinc Filter Clipping Limit 60g Range Positive/Negative and Sinc Filter Clipping Limit 120g Range Positive/Negative and Sinc Filter Clipping Limit 240g Range Positive/Negative and Sinc Filter Clipping Limit 480g Range Positive/Negative * * * *
VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified.
Symbol
gST10_60X gST10_120X gST10_240X gST10_480X gg-cell_Clip60X gg-cell_Clip120X gg-cell_Clip240X gg-cell_Clip480X gADC_Clip60X gADC_Clip120X gADC_Clip240X gADC_Clip480X
Min
120 40 56 8
Typ
-- -- -- --
Max
280 160 184 112
Units
LSB LSB LSB LSB (3) (3) (3) (3)
79
400
456
500
g
(9)
80
400
456
500
g
(9)
81
1750
2065
2300
g
(9)
82
1750
2065
2300
g
(9)
83
191
210
233
g
(9)
84
353
380
410
g
(9)
85
928
1055
1218
g
(9)
86
1690
1879
2106
g
(9)
MMA52xxWR Sensors Freescale Semiconductor Preliminary 7
2.6
#
87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
Dynamic Electrical Characteristics - PSI5
Characteristic
Initialization Timing Phase 1 Phase 2 (10-Bit, Synchronous Mode, k = 4) Phase 2 (8-Bit, Synchronous Mode, k = 8) Phase 2 (10-Bit, Asynchronous Mode 0, k = 8) Phase 2 (8-Bit, Asynchronous Mode 0, k = 16) Phase 3 (10-Bit, Synchronous Mode, ST_RPT = 0) Phase 3 (8-Bit, Synchronous Mode, ST_RPT = 0) Phase 3 (10-Bit, Asynchronous Mode 0, ST_RPT = 0) Phase 3 (8-Bit, Asynchronous Mode 0, ST_RPT = 0) Offset Cancellation Stage 1 Operating Time Offset Cancellation Stage 2 Operating Time Self-Test Stage 1 Operating Time Self-Test Stage 2 Operating Time Self-Test Stage 3 Operating Time Self-Test Repetitions Programming Mode Entry Window Synchronization Pulse (Figure 5, Figure 28 and Figure 32) Reset to first sync pulse (Program Mode Entry) Reset to first sync pulse (Normal Mode) Sync Pulse Period Sync Pulse Width Sync Pulse Reference LPF time constant Sync Pulse Reference Discharge Start Time Sync Pulse Reference Discharge Activation Time Sync Pulse Detection Disable Time (BLANKTIME = 0) Analog Delay of Sync Pulse Detection Sync Pulse Pull-down Function Delay Time Sync Pulse Pull-down Function Activate Time Sync Pulse Detection Jitter Data Transmission Single Bit Time (PSI5 Low Bit Rate) Data Transmission Single Bit Time (PSI5 High Bit Rate) Modulation Current (20% to 80% of IMOD - IIDLE) Rise Time Fall Time Position of bit transition (PSI5 Low Baud Rate) Position of bit transition (PSI5 High Baud Rate) Asynchronous Response Time Time Slots Minimum Programmed Time Slot (TIMESLOTx = 0x001) Maximum Programmed Time Slot (TIMESLOTx = 0x3FF) Default Time Slot (TIMESLOTx = 0x000) Time Slot Resolution Sync Pulse to Daisy Chain Default Time Slot 1 Sync Pulse to Daisy Chain Default Time Slot 2 Sync Pulse to Daisy Chain Default Time Slot 3 Sync Pulse to Daisy Chain Programming Time Slot Data Interpolation Latency (Figure 35, Figure 36) Data Setup Time - Synchronous Mode (Figure 36) Data Setup Time - Double Sample Rate Mode (Figure 37) Data Setup Time - 16-bit Resolution Mode (Figure 39) Programming Mode Timing Programming Mode Sync Pulse Period Programming Mode Command Timeout OTP Write Command to VCC = VPP OTP Write CMD Response to OTP programming start Time to program one OTP bit * * * * *
VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified
Symbol
tPSI5_INIT1 tPSI5_INIT2_10s tPSI5_INIT2_8s tPSI5_INIT2_10a0 tPSI5_INIT2_8a0 tPSI5_INIT3_10s tPSI5_INIT3_8s tPSI5_INIT3_10a0 tPSI5_INIT3_8a0 tOC1 tOC2 tST1 tST2 tST3 ST_RPT tPME
Min
Typ
532000 / fOSC 256 * tS-S 288 * tS-S 512 * tASYNC 576 * tASYNC 2 * tS-S 2 * tS-S 19 * tASYNC 2 * tASYNC 320000 / fOSC 280000 / fOSC 128000 / fOSC 128000 / fOSC 128000 / fOSC -- 300000 / fOSC
Max
Units
s s s s s s s s s s s s s s s (7) (7) (7) (7) (7) (7,12) (7,12) (7,12) (7,12) (7) (7) (7) (7) (7) (7,12) (7)
-- -- -- -- -- -- -- -- -- -- -- -- -- 0 --
-- -- -- -- -- -- -- -- -- -- -- -- -- 5 --
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
tRS_PM tRS tS-S tSYNC tSYNC_LPF tSYNC_LPF_RST_ST tSYNC_LPF_RST tSYNC_OFF_500 tA_SYNC_DLY tPD_DLY tPD_ON tSYNC_JIT tBIT_LOW tBIT_HI
58 tPSI5_INIT1 tSYNC_OFF 9 120 -- -- -- 50 -- -- 0 7.6000 4.9875
-- -- -- -- 280 66 /fOSC 616 /fOSC 1810 / fOSC -- 74 / fOSC 64 / fOSC -- 8.0000 5.2500
-- -- -- -- -- -- -- -- 600 -- -- 2 / fOSC 8.4000 5.5125
ms s s s s s s s ns s s s s s
(7) (7) (7) (7) (9) (7) (7) (7) (9) (7) (7) (7) (7) (7)
tRISE tFALL tBittrans_LowBaud tBittrans_HighBaud tASYNC
324 324 49 47 --
463 463 50 ae 912 / fOSC
602 602 51 53 ae
ns ns % % s
(3) (3) (7) (7) (7)
122 123 124 125 126 127 128 129
*
tTIMESLOTx_MIN tTIMESLOTx_MAX tTIMESLOT_DFLT tTIMESLOTx_RES tTIMESLOT_DC1 tTIMESLOT_DC2 tTIMESLOT_DC3 tTIMESLOT_DCP tLAT_INTERP tDATASETUP_synch tDATASETUP_double tDATASETUP_16
-- -- -- -- -- -- -- -- 64 / fOSC 48 / fOSC 48 / fOSC 48 / fOSC
2 / fOSC 2046 / fOSC 186 / fOSC 2 / fOSC 186 / fOSC 768 / fOSC 1400 / fOSC 186 / fOSC -- -- -- --
-- -- -- -- -- -- -- -- 65 / fOSC 56 / fOSC 60 / fOSC 60 / fOSC
s s s s/LSB s s s s s s s s
(7,9) (3,7) (3,7) (7) (7) (7) (7) (7) (7) (7) (7) (7)
130 131
132 133 134 135 136
tS-S_PM_L tPM_TIMEOUT tPROG_HOLD tPROG_DELAY tPROG_BIT
495 -- -- -- 64
500 4 * tS-S_PM -- -- --
505 -- 20 250 O
s s s s s
(7) (7) (7) (7) (7)
MMA52xxWR Preliminary 8 Sensors Freescale Semiconductor
2.7
#
137 138 139 140 141
Dynamic Electrical Characteristics - Signal Chain
Characteristic
Internal Oscillator Frequency DSP Low-Pass Filter (Note15) Cutoff frequency LPF0 (referenced to 0 Hz) Filter Order LPF0 Cutoff frequency LPF1 (referenced to 0 Hz) Filter Order LPF1 DSP Offset Cancellation Low Pass Filter (Note 15) Offset Cancellation Low Pass Filter Input Sample Rate Stage 1 Cutoff frequency, Start-up Phase 1 Stage 1 Filter Order, Start-up Phase 1 Stage 2 Cutoff frequency, Start-up Phase 1 Stage 2 Filter Order, Start-up Phase 1 Cutoff frequency, Option 0 Filter Order, Option 0 Cutoff frequency, Option 1 Filter Order, Option 1 Cutoff frequency, Option 2 Filter Order, Option 2 Offset Cancellation Output Update Rate (8-Bit Mode) Offset Cancellation Output Step Size (8-Bit Mode) Offset Cancellation Output Update Rate (10-Bit Mode) Offset Cancellation Output Step Size (10-Bit Mode) Offset Monitor Update Frequency Offset Monitor Count Limit Offset Monitor Counter Size Sensing Element Natural Frequency 60g 120g 240g 480g Sensing Element Rolloff Frequency (-3db) 60g 120g 240g 480g Sensing Element Damping Ratio 60g 120g 240g 480g Sensing Element Delay (@100Hz) 60g 120g 240g 480g Package Resonance Frequency *
VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified
Symbol
fOSC fC_LPF0 OLPF0 fC_LPF1 OLPF1 tOC_SampleRate fC_OC10 OOC10 fC_OC03 OOC03 fC_OC0 OOC0 fC_OC1 OOC1 fC_OC2 OOC2 tOffRate_8 OFFStep_8 tOffRate_10 OFFStep_10 OFFMONOSC OFFMONCNTLIMIT OFFMONCNTSIZE fgcell_X60 fgcell_X120 fgcell_X240 fgcell_X480 fgcell_X60 fgcell_X120 fgcell_X240 fgcell_X480 gcell_X60 gcell_X120 gcell_X240 gcell_X480
Min
3.80
Typ
4
Max
4.20
Units
MHz (1)
* * * *
400 3 400 4
Hz 1 Hz 1
(7) (7) (7) (7)
142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157

256 10.0 1 0.300 1 0.100 1 0.040 1 fOSC / 2e6 0.125 fOSC / 2e6 0.5 fOSC/2000 4096 8192

s Hz 1 Hz 1 Hz 1 Hz 1 s LSB s LSB Hz 1 1
(7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7)
158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174
12651 12651 26000 26000 938 938 3952 3952 2.760 2.760 1.260 1.260 63 63 13 13 100
13274 13274 27413 27413 1591 1591 6770 6770 4.220 4.220 2.280 2.280 101 101 25 25
13871 13871 28700 28700 2592 2592 14370 14370 6.770 6.770 3.602 3.602 170 170 40 40
Hz Hz Hz Hz Hz Hz Hz Hz s s s s kHz
(9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9)
fgcell_delay_X60 fgcell_delay_X120 fgcell_delay_X240 fgcell_delay_X480 fPackage
MMA52xxWR Sensors Freescale Semiconductor Preliminary 9
2.8
#
175 176
Dynamic Electrical Characteristics - Supply and SPI
Characteristic
Quiescent Current Settling Time (Power Applied to Iq = IIDLE +/- 2mA) Reset Recovery Internal Delay (After internal POR) VCC Micro-cut (CBUF=CREG=CREGA=1F) Survival Time (Vcc disconnect without Reset, CBUF=CREG=CREGA=700nF) Survival Time (Vcc disconnect without Reset, CBUF=CREG=CREGA=1F) Reset Time (Vcc disconnect above which Reset is guaranteed) VBUF, Capacitor Monitor Disconnect Time (Figure 10) POR to first Capacitor Test Disconnect Disconnect Time (Figure 10) Disconnect Delay, Asynchronous Mode (Figure 10) Disconnect Delay, Synchronous Mode (Figure 11) VREG, VREGA Capacitor Monitor POR to first Capacitor Test Disconnect Disconnect Time Disconnect Rate Serial Interface Timing (See Figure 7, CDOUT 80pF, RDOUT 10k) Clock (SCLK) period (10% of VCC to 10% of VCC) Clock (SCLK) high time (90% of VCC to 90% of VCC) Clock (SCLK) low time (10% of VCC to 10% of VCC) Clock (SCLK) rise time (10% of VCC to 90% of VCC) Clock (SCLK) fall time (90% of VCC to 10% of VCC) CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC) CS asserted to DOUT valid (CS = 10% of VCC to DOUT = 10/90% of VCC) Data setup time (DIN = 10/90% of VCC to SCLK = 10% of VCC) DIN Data hold time (SCLK = 90% of VCC to DIN = 10/90% of VCC) DOUT Data hold time (SCLK = 90% of VCC to DOUT = 10/90% of VCC) SCLK low to data valid (SCLK = 10% of VCC to DOUT = 10/90% of VCC) SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC) CS high to DOUT disable (CS = 90% of VCC to DOUT = Hi Z) CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)
VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified
Symbol
tSET tINT_INIT tVCC_MICROCUTmi
n
Min

Typ
16000 / fOSC
Max
5
Units
ms s (3) (7)
177 178 179
tVCC_MICROCUT tVCC_RESET tPOR_CAPTEST tCAPTEST_TIME tCAPTEST_ADLY tCAPTEST_SDLY tPOR_CAPTEST tCAPTEST_TIME tCAPTEST_RATE tSCLK tSCLKH tSCLKL tSCLKR tSCLKF tLEAD tACCESS tSETUP tHOLD_IN tHOLD_OUT tVALID tLAG tDISABLE tCSN
30 50

1000
s s s
(3) (3) (3)
180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200

12000/fOSC 6 / fOSC 688 / fOSC 72 / fOSC 12000 / fOSC 6 / fOSC 256 / fOSC 15 15
40 28 60 50 60
s s s s s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(7) (7) (7) (7) (7) (7) (7) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9)
320 120 120 60 20 10 0 60 1000
1. Parameters tested 100% at final test. 2. Parameters tested 100% at wafer probe. 3. Verified by characterization 4. * Indicates critical characteristic. 5. Verified by qualification testing. 6. Parameters verified by pass/fail testing in production. 7. Functionality verified 100% via boundary scan. (Timing is directly determined by internal oscillator frequency.) 8. N/A. 9. Guaranteed by design. 10. N/A. 11. Measured at VCC pin; VSYNC guaranteed across full VIDLE range. 12. Self-Test repeats on failure up to a ST_RPTMAX times before transmitting Sensor Error Message 13. N/A. 14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad. 15. Filter cut-off frequencies are directly dependent upon the internal oscillator frequency.
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tRS VSYNC tSYNC
tS-S
VIDLE VCC GND Figure 5. Sync Pulse Characteristics VSYNC
VCC_UV_f + VCC_HYST VCC_UV_f VCC VBUF_UV_f + VBUF_HYST VBUF_UV_f VBUF VREG_UV_f + VREG_HYST VREG_UV_f VREG VREGA_UV_f+VREGA_HYST VREGA_UV_f VREG POR Response Terminated if in process
Time
Figure 6. Power-Up Timing
CS
tLEAD tSCLKR tSCLK tSCLKF tSCLKH tCSN
SCLK
tSCLKL tACCESS tVALID tHOLD_OUT tLAG tDISABLE
DOUT
tHOLD_IN tSETUP
DIN Figure 7. Serial Interface Timing MMA52xxWR Sensors Freescale Semiconductor Preliminary 11
3
3.1
FUNCTIONAL DESCRIPTION
User Accessible Data Array
A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable block, an OTP user programmable block, and read only registers for device status. The OTP blocks incorporate independent CRC circuitry for fault detection (reference Section 3.2). Portions of the factory programmable array are reserved for factory-programmed trim values. The user accessible data is shown in Table 2. Table 2. User Accessible Data
Byte Addr (XLong Msg)
$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C
Register
Nibble Addr (Long Msg)
$01 $03 $05 $07 $09 $0B $0D $0F $11 $13 $15 $17 $19
Bit Function 7
SN[7] SN[15] SN[23] SN[31] 0 LOCK_U
6
SN[6] SN[14] SN[22] SN[30] 0 PCM
5
SN[5] SN[13] SN[21] SN[29] 1 SYNC_PD LPF[1]
4
SN[4] SN[12] SN[20] SN[28] 0 LATENCY LPF[0]
Nibble Addr (Long Msg)
$00 $02 $04 $06 $08 $0A $0C $0E $10 $12 $14 $16 $18
Bit Function Type 3
SN[3] SN[11] SN[19] SN[27] 0 DATASIZE
2
SN[2] SN[10] SN[18] SN[26] RNG[2] BLANKTIME
1
SN[1] SN[9] SN[17] SN[25] RNG[1] P_CRC
0
SN[0] SN[8] SN[16] SN[24] RNG[0] BAUD F, R
SN0 SN1 SN2 SN3 DEVCFG1 DEVCFG2 DEVCFG3 DEVCFG4 DEVCFG5 DEVCFG6 DEVCFG7 DEVCFG8 SC
TRANS_MD[1] TRANS_MD[0]
TIMESLOTB[9] TIMESLOTB[8] TIMESLOTA[9] TIMESLOTA[8] TIMESLOTA[3] TIMESLOTA[2] TIMESLOTA[1] TIMESLOTA[0] TIMESLOTB[3] TIMESLOTB[2] TIMESLOTB[1] TIMESLOTB[0] U_REV[3] YEAR[3] DAY[3] OC_INIT_B U_REV[2] YEAR[2] DAY[2] IDEF_B U_REV[1] YEAR[1] DAY[1] OFF_B U_REV[0] YEAR[0] DAY[0] TEMPF_B R U, R
TIMESLOTA[7] TIMESLOTA[6] TIMESLOTA[5] TIMESLOTA[4] TIMESLOTB[7] TIMESLOTB[6] TIMESLOTB[5] TIMESLOTB[4] INIT2_EXT MONTH[3] CRC_U[2] 0 ASYNC MONTH[2] CRC_U[1] TM_B U_DIR[1] MONTH[1] CRC_U[0] RESERVED U_DIR[0] MONTH[0] DAY[4] IDEN_B
Type codes F: Freescale programmed OTP location U: User programmable OTP location via PSI5 R: Readable register via PSI5
3.1.1
Device Serial Number Registers
A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial number is composed of the following information:
Bit Range SN[12:0] SN[31:13] Content Serial Number Lot Number
Serial numbers begin at 1 for all produced devices in each lot and are sequentially assigned. Lot numbers begin at 1 and are sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. The serial number registers are included in the factory programmed OTP CRC verification. Reference Section 3.2.1 for details regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or performance, and are only used for traceability purposes.
3.1.2
Factory Configuration Register (DEVCFG1)
The factory configuration register is a factory programmed, read only register which contains user specific device configuration information. The factory configuration register is included in the factory programmed OTP CRC verification.
Location Address $04 Register DEVCFG1 7 0 0 6 0 0 5 1 1 4 0 0 Bit 3 0 0 2 RNG[2] 0 1 RNG[1] 0 0 RNG[0] 0
Factory Default
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3.1.2.1
Range Indication Bits (RNG[2:0])
The range indication bits are factory programmed and indicate the full scale range of the device as shown below.
Full-Scale Acceleration Range Reserved 60g Reserved 120 g Reserved 240 g Reserved 480 g PSI5 Init Data Transmission (D9) Reference Table 12 0001 0111 0010 1000 0011 1001 0100 1010
RNG[2] 0 0 0 0 1 1 1 1
RNG[1] 0 0 1 1 0 0 1 1
RNG[0] 0 1 0 1 0 1 0 1
Axis N/A X N/A X N/A X N/A X
g-Cell Design N/A M64S N/A M64S N/A M95V N/A M95V
3.1.3
Device Configuration 2 Register (DEVCFG2)
Device configuration register 2 is a user programmable OTP register that contains device configuration information.
Location Address $05 Register DEVCFG2 7 LOCK_U 0 6 PCM 0 5 SYNC_PD 0 4 LATENCY 0 Bit 3 DATASIZE 0 2 BLANKTIME 0 1 P_CRC 0 0 BAUD 0
Factory Default
3.1.3.1
User Configuration Lock Bit (LOCK_U)
The LOCK_U bit allows the user to prevent writes to the user configuration array once programming is completed. If the LOCK_U bit is written to `1' when a PSI5 "Execute Programming of NVM" command is executed, the LOCK_U OTP bit will be programmed. Upon completion of the OTP programming, an OTP readout will be executed, locking the array from future OTP writes. The User Programmable OTP Array CRC Verification is also activated (Reference Section 3.2.2).
3.1.3.2
PCM Enable Bit (PCM)
The PCM bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code Modulated signal proportional to the acceleration response. Reference Section 3.5.3.7 for more information regarding the PCM output. When the PCM bit is cleared, the PCM output pin is actively pulled low.
PCM 0 1 PCM Output Actively Pulled Low PCM Signal Enabled
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3.1.3.3
Sync Pulse Pull-Down Enable Bit (SYNC_PD)
The sync pulse pull-down enable bit selects if the sync pulse pull-down is enabled once a sync pulse is detected. Reference Section 4.2.1.2 for more information regarding the sync pulse pull-down.
SYNC_PD 0 1 Sync Pulse Pull-Down Disabled Enabled
If Daisy Chain Mode is enabled, the Sync Pulse Pull-Down is enabled as listed below:
SYNC_PD 0 1 1 1 1 Daisy Chain Address Programmed x No Yes Yes Yes "Run Mode" Command Received x x No Yes Yes Daisy Chain Address = `001' x x x No Yes Sync Pulse Pull-Down Disabled Enabled Disabled Disabled Enabled
3.1.3.4
Latency Selection Bit (LATENCY)
The latency selection bit selects between one of two data latency methods to accommodate synchronized sampling or simultaneous sampling. Reference Section 4.5 for more information regarding latency and data synchronization.
Latency 0 1 Data Latency Simultaneous Sampling Mode (Latency relative to sync pulse) Synchronous Sampling Mode (Latency relative to Time Slot)
3.1.3.5
Data Size Selection Bit (DATASIZE)
The data size selection bit selects one of two data lengths for the PSI5 response message as shown below.
DATASIZE 0 1 Data Length 10 Bits 8 Bits
3.1.3.6
PSI5 Sync Pulse Blanking Time Selection Bit (BLANKTIME)
The PSI5 sync pulse blanking time selection bit selects the timing for ignoring sync pulses after successful reception of a sync pulse. Reference Section 4.2.1.1 for details regarding sync pulse detection and blanking.
BLANKTIME 0 1 Blanking Time Method Maximum of tSYNC_OFF_500 or Response Transmission Complete Blanking Time determined by end of response transmission for programmed time slot
3.1.3.7
PSI5 Response Message Error Detection Selection Bit (P_CRC)
The PSI5 response message error detection selection bit selects either even parity, or a 3-Bit CRC for error detection of the PSI5 response message. Reference Section 4.3.3 for details regarding response message error detection.
P_CRC 0 1 Parity or CRC Parity CRC
Note: The PSI5 specification recommends parity for data lengths of 10 bits or less.
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3.1.3.8
Baud Rate Selection Bit (BAUD)
The baud rate selection bit selects one of two PSI5 baud rates as shown below. Reference Section 2.6 for baud rate timing specifications.
BAUD 0 1 Baud Rate Low Baud Rate (125 kBaud) High Baud Rate (190.5 kBaud)
3.1.4
Device Configuration Registers (DEVCFG3, DEVCFG4, DEVCFG5)
Device configuration registers 3, 4, and 5 are user programmable OTP registers which contain device configuration information.
Location Address $06 $07 $08 Register DEVCFG3 DEVCFG4 DEVCFG5 7 TRANS_MD[1] 6 TRANS_MD[0] 5 LPF[1] 4 LPF[0] Bit 3 2 1 0
TIMESLOTB[9] TIMESLOTB[8] TIMESLOTA[9] TIMESLOTA[8]
TIMESLOTA[7] TIMESLOTA[6] TIMESLOTA[5] TIMESLOTA[4] TIMESLOTA[3] TIMESLOTA[2] TIMESLOTA[1] TIMESLOTA[0] TIMESLOTB[7] TIMESLOTB[6] TIMESLOTB[5] TIMESLOTB[4] TIMESLOTB[3] TIMESLOTB[2] TIMESLOTB[1] TIMESLOTB[0] 0 0 0 0 0 0 0 0
Factory Default
3.1.4.1
PSI5 Transmission Mode Selection Bits (TRANS_MD[1:0])
The PSI5 transmission mode selection bits select the PSI5 transmission mode as shown below.
TRANS_MD[1] 0 0 1 1 TRANS_MD[0] 0 1 0 1 Operating Mode Normal Mode (Asynchronous or Parallel, Synchronous) Synchronous Double Sample Rate Mode 16-bit Resolution Mode (2 10-bit Responses) Daisy Chain Mode Reference Section 4.5.1 Section 4.5.1.3 Section 4.5.2 Section 4.5.4
3.1.4.2
Low-Pass Filter Selection Bit (LPF[1:0])
The low pass filter selection bits select the low pass filter for the acceleration signal as described below:
LPF[1] 0 0 1 1 LPF[0] 0 1 0 1 Low Pass Filter Selected 400 Hz, 3 Pole 400 Hz, 4 Pole Reserved Reserved
3.1.4.3
TimeSlot Selection Bits (TIMESLOTx[9:0])
The timeslot selection bits select the time slot(s) to be used for data transmission. Reference Section 4.5 for details regarding PSI5 transmission modes and time slots. Accepted time slot values are 0.5 s to 511.5 s in 0.5 s increments. Care must be taken to prevent from programming time slots which violate the PSI5 Version 1.3 specification, or time slots which will cause data contention.
TIMESLOTx[9:0] 00 0000 0000 1 Non-Zero N/A ASYNC Bit 0 Time Slot Default Time Slot (tTIMESLOT_DFLT) from start of Sync Pulse (tTRIG) Asynchronous Mode TimeSlot Definition from start of Sync Pulse (tTRIG) in 0.5s Increments Reference Section 4.5 Section 4.5.1.1 Section 4.5
Note: TIMESLOTB is only used for Synchronous Double Sample Rate Mode and 16-Bit Resolution Mode.
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3.1.5
Device Configuration Registers 6, 7, and 8 (DEVCFG6, DEVCFG7, DEVCFG8)
Device configuration registers 6, 7 and 8 are user programmable OTP registers which contain device configuration and user specific manufacturing information. The user specific manufacturing information bits have no impact on the performance, but are transmitted during the PSI5 initialization phase 2 in 10-bit mode.
Location Address $09 $0A $0B Register DEVCFG6 DEVCFG7 DEVCFG8 7 INIT2_EXT MONTH[3] CRC_U[2] 0 6 ASYNC MONTH[2] CRC_U[1] 0 5 U_DIR[1] MONTH[1] CRC_U[0] 0 4 U_DIR[0] MONTH[0] DAY[4] 0 Bit 3 U_REV[3] YEAR[3] DAY[3] 0 2 U_REV[2] YEAR[2] DAY[2] 0 1 U_REV[1] YEAR[1] DAY[1] 0 0 U_REV[0] YEAR[0] DAY[0] 0
Factory Default
3.1.5.1
Initialization Phase 2 Data Extension Bit (INIT2_EXT)
The initialization phase 2 data extension bit enables or disables data transmission in data fields D27 through D32 of PSI5 Initialization Phase 2 as shown below.
INIT2_EXT 0 1 Description D27 through D32 are set to "0000" D27 through D32 are transmitted as defined in Section 4.4.2.1
3.1.5.2 3.1.5.3
Asynchronous Mode Bit (ASYNC) User Sensing Direction (U_DIR[1:0])
The asynchronous mode bit enables asynchronous data transmission as described in Section 3.1.4.3.
The user sensing direction registers are user programmable OTP registers which contain the module level sensing direction. This data is transmitted to the main ECU during PSI5 initialization phase 2 in 10-bit mode, as described in Section 4.4.2.1.
U_DIR[1] 0 0 1 1 U_DIR[0] 0 1 0 1 Module Sensing Direction As Defined in AKLV27 Connector Direction () Bushing Direction () Perpendicular to and () Not used PSI5 Init Data Transmission (D8) Reference Table 12 0000 0100 1000 1100
3.1.5.4
User Product Revision (U_REV[3:0])
The user product revision registers are user programmable OTP registers which contain the module production revision. The device supports up to 16 product revisions. This data is transmitted to the main ECU during PSI5 initialization phase 2 in 10-bit mode, as described in Section 4.4.2.1.
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3.1.5.5
User Production Date Information (YEAR[3:0], MONTH[3:0], DAY[4:0)
The user production date information registers are user programmable OTP registers which contain the module production date. The table below shows the relationship between the stored values and the production date.
Programmed Value YEAR[3:0] 0000 * * * 1111 MONTH[3:0] 0000 0001 * * * 1100 * * * 1111 DAY[4:0] 00000 00001 * * * 11111 N/A Day 1 * * * Day 31 N/A January * * * December * * * N/A Day 00000 00001 * * * 11111 2009 * * * 2024 Month 0000 0001 * * * 1100 * * * N/A Decoded Value Year 0001001 * * * 0011000 Julian Date Value
The Julian date value is transmitted to the main ECU during PSI5 initialization phase 2 in 10-bit mode, as described in Section 4.4.2.2.
3.1.5.6
User Configuration CRC (CRC_U[2:0])
The user configuration CRC bits contain the 3-bit CRC used for verification of the user programmable OTP array. Reference Section 3.2.2 for information regarding the CRC for the user programmable OTP array.
3.1.6
Status Check Register (SC)
Location Bit 7 0 6 TM_B 5 RESERVED 4 IDEN_B 3 OC_INIT_B 2 IDEF_B 1 OFF_B 0 TEMPF_B
The status check register is a read-only register containing device status information.
Address $0C
Register SC
3.1.6.1
Test Mode Flag (TM_B)
The test mode bit is cleared if the device is in test mode.
TM_B 0 1 Operating Mode Test Mode is active Test Mode is not active
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3.1.6.2
Internal Data Error Flag (IDEN_B)
The internal data error bit is cleared if a register data CRC fault is detected in the user accessible OTP array. A device reset is required to clear the error.
IDEN_B 0 1 Error Condition CRC error in user programmable OTP array No error detected
3.1.6.3
Offset Cancellation Init Status Flag (OC_INIT_B)
The offset cancellation initialization status bit is set once the offset cancellation initialization process is complete, and the filter has switched to normal mode.
OC_INIT_B 0 1 Error Condition Offset Cancellation in initialization Offset Cancellation initialization complete (tOC1 and tOC2 expired)
3.1.6.4
Internal Factory Data Error Flag (IDEF_B)
The internal factory data error bit is cleared if a register data CRC fault is detected in the factory programmable OTP array. A device reset is required to clear the error.
IDEF_B 0 1 Error Condition CRC error in factory programmable OTP array No error detected
3.1.6.5
Offset Error Flag (OFF_B)
The offset error flag is cleared if the acceleration signal reaches the offset limit.
OFF_B 0 1 Error Condition Offset error detected No error detected
3.1.6.6
Temperature Error Flag (TEMPF_B)
The temperature error flag is cleared if an over or under temperature condition exists.
TEMPF_B 0 1 Error Condition Over- or Under-Temperature error condition detected No error detected
3.2
3.2.1
OTP Array CRC Verification
Factory Programmed OTP Array CRC Verification
The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the factory programmed array is locked. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = `111'. Once the CRC verification is enabled, the CRC is continuously calculated on all bits in registers $00, $01, $02, $03, and $04 and on the factory programmable device configuration bits with the exception of the factory lock bit. Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The calculated CRC is then compared against the stored 3 bit CRC. If a CRC error is detected in the OTP array, the IDEF_B bit is cleared in the SC register. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
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3.2.2
User Programmable OTP Array CRC Verification
The user programmable OTP array is independently verified for errors with a 3-bit CRC. The CRC verification is enabled only when the LOCK_U bit in the user data register array is set after POR, or after a PSI5 Programming Mode "Execute Programming of NVM" command. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = `111'. The calculated CRC is compared against a user programmable 3-bit CRC, CRC_U[2:0], which is also included in the user programmable array. Once the CRC verification is enabled, the CRC is continuously calculated on all bits in registers $05, $06, $07, $08, $09, $0A, and $0B with the exception of the LOCK_U bit and the CRC_U[2:0] bits. Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The calculated CRC is then compared against the CRC_U[2:0] bits. If a CRC mismatch is detected, the IDEN_B bit is cleared in the SC register. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
3.3
Voltage Regulators
The device derives its internal supply voltage from the VCC and VSS pins. Separate internal voltage regulators are used for the analog (VREGA) and digital circuitry (VREG). The analog and digital regulators are supplied by a buffer regulator (VBUF) to provide immunity from EMC and supply dropouts on VCC. External filter capacitors are required, as shown in Figure 1. The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the internal voltages have increased above the undervoltage detection thresholds. The voltage monitor asserts internal reset when the external supply or internally regulated voltages fall below the undervoltage detection thresholds. A reference generator provides a reference voltage for the converter.
VCC
VREF VBUF VOLTAGE REGULATOR
VBUF VOLTAGE REGULATOR
VREGA = 2.50 V
VREGA
VREGA
TRIM BANDGAP REFERENCE TRIM
VREF
BIAS GENERATOR TRIM
OSCILLATOR TRIM CONVERTER
REFERENCE VREF_MOD = 1.250 V GENERATOR
VBUF VREF
OTP ARRAY
VREG = 2.50 V
VOLTAGE REGULATOR
VREG DIGITAL LOGIC
DSP
VCC
COMPARATOR
Micro-cut
VBUF
COMPARATOR
POR VREG VREGA VREF
COMPARATOR
COMPARATOR
Figure 8. Voltage Regulation and Monitoring
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VBUF, VREG, and VREGA Regulator Capacitor The internal regulators require an external capacitor between each of the regulator pins (VBUF, VREG, or VREGA) and the associated the VSS / VSSA pin for stability. Figure 1 shows the recommended types and values for each of these capacitors. 3.3.2 VCC, VBUF, VREG, and VREGA Undervoltage Monitor
A circuit is incorporated to monitor the supply voltage (VCC) and all internally regulated voltages (VBUF, VREG, and VREGA). If any of internal regulator voltages fall below the specified undervoltage thresholds in Section 2, the device will be reset. If VCC falls below the specified threshold, PSI5 transmissions are terminated for the present response. Once the supply returns above the threshold, the device will respond to the next detected sync pulse. Reference Figure 9.
3.3.1
VCC micro-cut occurs
VCC
VBUF
VCC undervoltage detected
VREG
VREGA
Response Terminated
IDATA
POR Time
Figure 9. VCC Micro-Cut Response
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3.3.3
VBUF, VREG, and VREGA Capacitance Monitor A monitor circuit is incorporated to ensure predictable operation if the connection to the external VBUF, VREG, or VREGA, capacitor becomes open.
In asynchronous mode, the VBUF regulator is disabled tCAPTEST_ADLY seconds after each data transmission for a duration of tCAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold, forcing a device reset. In synchronous mode, the VBUF regulator is disabled tCAPTEST_SDLY seconds after each sync pulse for a duration of tCAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold, forcing a device reset. The VREG and VREGA regulators are disabled at a continuous rate (tCAPTEST_RATE), for a duration of tCAPTEST_TIME seconds. If either external capacitor is not present, the associated regulator voltage will fall below the internal reset threshold, forcing a device reset.
IDATA
tCAPTEST_ADLY
tCAPTEST_TIME
CAP_Test
VBUF
Capacitor Present Capacitor Open
VBUF_UV_f
POR
Time
Figure 10. VBUF Capacitor Monitor - Asynchronous Mode
VCC
tCAPTEST_SDLY tTRIG
tCAPTEST_TIME
CAP_Test
VBUF
Capacitor Present
VBUF_UV_f
Capacitor Open
POR
Time
Figure 11. VBUF Capacitor Monitor - Synchronous Mode
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tCAPTEST_RATE tCAPTEST_TIME
CAP_Test
VREG VPORVREG_f POR
Capacitor Present
Capacitor Open
Time Figure 12. VREG Capacitor Monitor
tCAPTEST_RATE tCAPTEST_TIME
CAP_Test
VREGA VPORREGA_f POR
Capacitor Present
Capacitor Open
Time Figure 13. VREGA Capacitor Monitor
3.4 3.5
3.5.1
Internal Oscillator Acceleration Signal Path
Transducer
2 n H ( s ) = -------------------------------------------------------2 2 s + 2 n s + n
A factory trimmed oscillator is included as specified in Section 2.
The transducer is an overdamped mass-spring-damper system defined by the following transfer function:
where: = Damping Ratio n = Natural Frequency = 2 fn Reference Section 2.7 for transducer parameters.
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3.5.2
Converter
A sigma delta modulator converts the differential capacitance of the transducer to a 1 MHz data stream that is input to the DSP block.
g-CELL 1= CTOP CBOT C = CTOP - CBOT V = C x VX / CINT1 VX CINT1
FIRST INTEGRATOR z-1 1 - z-1 2
SECOND INTEGRATOR z-1 1 - z-1
1-BIT QUANTIZER _OUT ADC
1
2 DAC V = 2 x VREF
Figure 14. Converter Block Diagram
3.5.3
Digital Signal Processing Block
A digital signal processing (DSP) block is used to perform signal filtering and compensation. A diagram illustrating the signal processing flow within the DSP block is shown in Figure 15.
A _OUT
SINC FILTER
B
LOW PASS FILTER
C
COMPENSATION
D
DOWNSAMPLING
E
OFFSET OFFSET CANCELLATION CANCELLATION LOW PASS FILTER OUTPUT RATE LIMITING
F
OUTPUT H G SCALING INTERPOLATION OUTPUT
Figure 15. Signal Chain Diagram Table 3. Opuntia Signal Chain Characteristics
Description A B C D E F G 10-Bit Output Scaling H Interpolation 1 10 SD SINC Filter Low Pass Filter Compensation Down Sampling High Pass Filter DSP Sampling 16 10 4/fosc 64/fosc Section 3.5.3.5 Section 3.5.3.5 Sample Time (s) 1 16 16 16 16 16 Data Width (Bits) 1 20 26 26 26 26 4 4 4 4 Over Range (Bits Signal Width (Bits) 1 13 10 10 10 10 3 3 3 3 9 9 9 9 68/fosc Reference Section 3.5.3.3 Section 3.5.3.3 203/fosc Reference Section 3.5.3.2 Signal Noise (Bits) Signal Margin (Bits) Typical Block Latency Reference Section 3.5.2 Section 3.5.3.2 Section 3.5.3.2
MMA52xxWR Sensors Freescale Semiconductor Preliminary 23
3.5.3.1
Decimation Sinc Filter
The serial data stream produced by the converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 16.
3 1 - z - 16 H ( z ) = -----------------------------------16 x ( 1 - z - 1 )
Figure 16. Sinc Filter Response, tS = 16 s
MMA52xxWR Preliminary 24 Sensors Freescale Semiconductor
3.5.3.2
Low Pass Filter ( n 11 z 0 ) + ( n 12 z - 1 ) + ( n 13 z - 2 ) ( n 21 z 0 ) + ( n 22 z - 1 ) + ( n 23 z - 2 ) H ( z ) = a 0 ------------------------------------------------------------------------------------------------ -----------------------------------------------------------------------------------------------( d 11 z 0 ) + ( d 12 z - 1 ) + ( d 13 z - 2 ) ( d 11 z 0 ) + ( d 22 z - 1 ) + ( d 23 z - 2 )
Data from the Sinc filter is processed by an infinite impulse response (IIR) low pass filter.
The device provides the option for one of two low-pass filters. The filter is selected with the LPF[1:0] bits in the DEVCFG3 register. The filter selection options are listed in Section 3.1.4.2. Response parameters for the low-pass filter are specified in Section 2.7. Filter characteristics are illustrated in Figure 17 and Figure 18. Table 4. Low Pass Filter Coefficients
Description a0 n11 n12 400 Hz, 3-Pole LPF n13 n21 n22 n23 a0 n11 n12 400 Hz, 4-Pole LPF n13 n21 n22 n23 Filter Coefficients 5.189235225042199e-02 1.629077582099646e-03 1.630351547919014e-03 0 2.500977520825902e-01 4.999999235890745e-01 2.499023243303036e-01 3.143225986084408e-03 9.951105668343345e-04 2.003487780064749e-03 1.008466113720278e-03 2.516720624825626e-01 4.999888752940916e-01 2.483390622233452e-01 d11 d12 d13 d21 d22 d23 1.0 -1.892328151433503e+00 8.954713774195870e-01 1.0 -1.918978239761011e+00 9.229853042218408e-01 3392/fosc d11 d12 d13 d21 d22 d23 1.0 -9.481076477495780e-01 0 1.0 -1.915847097557409e+00 9.191065266874253e-01 2816/fosc Group Delay
Note: Low Pass Filter values do not include g-cell frequency response.
MMA52xxWR Sensors Freescale Semiconductor Preliminary 25
Figure 17. Low-Pass Filter Characteristics: fC = 400 Hz, 4-Pole, tS = 16 s
MMA52xxWR Preliminary 26 Sensors Freescale Semiconductor
Figure 18. Low-Pass Filter Characteristics: fC = 400 Hz, 3-Pole, tS = 16 s
MMA52xxWR Sensors Freescale Semiconductor Preliminary 27
3.5.3.3
Offset Cancellation
The device provides an optional offset cancellation circuit to remove internal offset error. A block diagram of the offset cancellation is shown in Figure 19.
INPUT DATA
OFFSET CANCELLATION LOW PASS FILTER n + ( n z-1 ) 1 2 a -----------------------------------0 d + ( d z-1 ) 1 2
INC/DEC
OUT
TO_OUTPUT SCALING
COUNTER
0.5 Hz (Derived from fOSC)
Input Data downsampled to 256s
OFFMONNEG
CLK
INC/DEC
OUT
OFF_ERR OFFMONCNTLIMIT
UP/DOWN
OFFMONPOS
COUNTER CLK
2 kHz (Derived from fOSC)
Figure 19. Offset Cancellation Block Diagram The transfer function for the offset LPF is:
no 1 + ( no 2 z - 1 ) H ( z ) = ao 0 ---------------------------------------------do 1 + ( do 2 z - 1 )
Response parameters are specified in Section 2 and the offset LPF coefficients are specified in Table 6. During start-up, two phases of the offset LPF are used to allow for fast convergence of the internal offset error during initialization. The timing and characteristics of each phase are shown in Table 5 and Table 6 and specified in Section 2. For more information regarding the startup timing, reference the PSI5 initialization information in Section 4.4. The offset low pass filter used in normal operation is selected by the OC_FILT bit as shown in Table 5. During the Initialization Self-Test phase, the offset cancellation circuit output value is frozen. During normal operation, output rate limiting is applied to the output of the high pass filter. Rate limiting updates the offset cancellation output by OFFStep_xx LSB every tOffRate_xx seconds. Table 5. Offset Cancellation Startup Characteristics and Timing
Offset Cancellation Start-Up Phase 1 2 Self-Test Complete Offset LPF 10 Hz 0.3 Hz 0.3 Hz 0.1 Hz Output Rate Limiting Bypassed Bypassed Bypassed (Frozen during ST2) Enabled Total Time for Phase 80 ms 70 ms 96 ms per Self-Test Sequence (up to 6 repeats) N/A
MMA52xxWR Preliminary 28 Sensors Freescale Semiconductor
Table 6. High Pass Filter Coefficients
Description ao0 10 Hz HPF no1 no2 ao0 0.3 Hz HPF no1 no2 ao0 0.1 Hz HPF no1 no2 ao0 0.04 Hz HPF no1 no2 0.015956938266754 0.499998132328277 0.499998132328277 0.000482380390167 0.499938218213271 0.499938218213271 0.0001608133316040 0.4999999403953552 0.4999999403953552 0.0000643134117126 0.4999999403953552 0.4999999403953552 do1 do2 1.0 -0.9999356269836426 3976ms do1 do2 1.0 -0.9998391270637512 1591ms do1 do2 1.0 -0.999517619609833 537.6 ms do1 do2 1.0 -0.984043061733246 16.384 ms Coefficients Group Delay
Figure 20. 10Hz Offset Cancellation Low Pass Filter Characteristics
MMA52xxWR Sensors Freescale Semiconductor Preliminary 29
Figure 21. 0.1 Hz Offset Cancellation Low Pass Filter Characteristics
3.5.3.4
Offset Monitor
The device includes an offset monitor circuit. The output of the single pole low pass filter in the offset cancellation block is continuously monitored against the offset limits specified in Section 2.4. An up/down counter is employed to count up If the output exceeds the limits, and to count down if the output is within the limits. The output of the counter is compared against the count limit OFFMONCNTLIMIT. If the counter exceeds the limit, the OFF_B flag in the SC register is cleared. The counter rails once the max counter value is reached (OFFMONCNTSIZE). The offset monitor is disabled during Initialization Phase1, Phase 2, and Phase 3.
3.5.3.5
Data Interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital signal processing chain is delayed one sample time. On detection of a sync pulse the transmitted data is interpolated from the 2 previous samples, resulting in a latency of one sample time, and a maximum signal jitter of 1/16 of a sample time. Reference Section 4.5 for more information regarding interpolation and data latency.
3.5.3.6
Output Scaling
The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-bit word which spans the acceleration range of the device. Figure 22 shows the method used to establish the output acceleration data word from the 26-bit DSP output.
Over Range D25 D24 D23 D22 D21 D20 D19 Signal D18 D17 D16 D15 D14 D13 D12 Noise D11 D10 D9 D8 ... Margin D2 D1 D0
8-bit Data Word 10-bit Data Word
D21 D21
D20 D20
D19 D19
D18 D18
D17 D17
D16 D16
D15 D15
D14 D14 D13 D12
Using Rounding Using Rounding
Figure 22. 10-Bit Output Scaling Diagram
MMA52xxWR Preliminary 30 Sensors Freescale Semiconductor
3.5.3.7
PCM Output Function
The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2 register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the 10-bit acceleration response is output onto the PCM pin. The PCM output is intended for test use only.
D[21:13] Output Scaling Section 3.5.3.6 9
A
CARRY
PCM
9 Bit ADDER 9 B SUM
D Q D Q D Q D Q D Q D Q DFF Q DFF Q DFF Q FF FF FF FF FF FF CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q
Sample updated every 16S
fCLK = 4 MHz 9
Figure 23. PCM Output Function Block Diagram
3.6
3.6.1
Overload Response
Overload Performance
The device is designed to operate within a specified range. Acceleration beyond that range (overload) impacts the output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent upon the overload frequency and amplitude. The g-cell is overdamped, providing the optimal design for overload performance. However, the performance of the device during an overload condition is affected by many other parameters, including: * g-cell damping * Non-linearity * Clipping limits * Symmetry Figure 24 shows the g-cell, ADC and output clipping of The device over frequency. The relevant parameters are specified in Section 2.
Acceleration (g) Region Clipped by Output LPFRolloff
g-cellRolloff
ll g-ce
Determined by g-cell roll-off and ADC clipping
by ped Clip ion Reg
gg-cell_Clip
gADC_Clip
to due rity ADC a rtion d by isto n-Line pe al D No Clip Sign and ion n of metry Reg io Reg Asym
Determined by g-cell
roll-off and full scale range
gRange_Norm Region of Interest fLPF Region of No Signal Distortion Beyond Specification fg-Cell 5kHz 10kHz Frequency (kHz)
Figure 24. Output Clipping Vs. Frequency
3.6.2
Sigma Delta Modulator Over Range Response
Over Range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the DSP. The converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates predictably under all cases of over range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. MMA52xxWR Sensors Freescale Semiconductor Preliminary 31
4
4.1
PSI5 LAYER AND PROTOCOL
Communication Interface Overview
The communication interface between a master device and the Opuntia is established via a PSI5 compatible 2-wire interface, with parallel or serial (daisy-chain) connections to the satellite modules. Figure 25 shows one possible system configuration for multiple satellite modules in parallel.
MASTER DEVICE
SATELLITE MODULE #1 MMA52xx VCC
VSS
Discrete Components
VCC IData VSS
VCC_OUT VSS_OUT SATELLITE MODULE #2
MMA52xx VCC
VSS
Discrete Components
VCC IData VSS
VCC_OUT VSS_OUT
Figure 25. PSI5 Satellite Interface Diagram
4.2
Data Transmission Physical Layer
The device uses a two wire interface for both its power supply (VCC), and data transmission. The PSI5 master supplies a preregulated voltage. Data transmissions and synchronization control from the PSI5 master to the device are accomplished via modulation of the supply voltage. Data transmissions from the device to the PSI5 master are accomplished via modulation of the current on the power supply line.
4.2.1
Synchronization Pulse
The PSI5 master modulates the supply voltage in the positive direction to provide synchronization of the satellite sensor data. Upon reception of a synchronization pulse, the device delays a specified period of time, called a time slot, before transmitting acceleration data. For more details regarding time slots, refer to Section 3.1.4, and Section 4.5.
SYNC PULSES VIDLE+ VSYNC VIDLE
GND IIDLE + IMOD
IIDLE
Figure 26. Synchronous Communication Overview
MMA52xxWR Preliminary 32 Sensors Freescale Semiconductor
4.2.1.1
Synchronization Pulse Detection
The Synchronization (Sync) pulse detection block generates a valid synchronization pulse signal following the detection of an externally generated Sync pulse. This signal resets the Sync pulse time reference (tTRIG), and initiates the timers associated with response messages. The supply voltage can vary throughout the specified range, so the external Sync pulses may have different absolute voltage levels. Thus, the Sync pulse detection threshold (VCC_SYNC) is dependent not only on the Sync pulse absolute voltage, but also on the supply voltage. Figure 27 shows a block diagram of the Sync pulse detection circuit.
VCC SYNC_OFF SYNC_OFFSET R VSYNC_REF
VSYNC_COMP
D COUNTER
CONTROL LOGIC SYNC_DET SYNC_LPF_RESET
SYNC_LPF
fOSC/2
SYNC_LPF_RESET
VSS
Figure 27. Synchronization Pulse Detection Circuit The start of a Sync pulse is detected when the comparator output is set (VSYNC exceeds VSYNC_REF). The comparator output is input into a counter, and the counter is updated at a fixed frequency of fOSC/2. At a fixed time after the initial sync pulse detection (tSYNC_LPF_RST_ST), the counter is compared against a limit (the minimum value of tSYNC). If the counter is above the limit, a valid sync pulse is detected. If the Sync pulse is valid, the following occur: 1. The valid Sync pulse detection signal is set. 2. The detection counter is reset and disabled for tSYNC_OFF (referenced from tTRIG). tSYNC_OFF is a user programmable option. Reference Section 3.1.3.6 for details on the selectable option, and Section 2.6 for timing specifications for each option. a. a. If BLANKTIME = `0', tSYNC_OFF = tSYNC_OFF_500 If BLANKTIME = `1', tSYNC_OFF=tSYNC_OFF_VAR= tTIMESLOT_DLYx + (2+DATASIZE+(P_CRC?3:1)) *tBIT_x
3. The Sync pulse detection low pass filter is reset for a specified time (tSYNC_LPF_RESET). If the Sync pulse is invalid, all timers are reset, and the detector becomes sensitive for the very next fSYNC_DET sample. The output of the comparator is monitored at the fOSC/2 frequency. Once the comparator output goes high, all of the internal timers are started, so that the tTRIG jitter is minimized.
MMA52xxWR Sensors Freescale Semiconductor Preliminary 33
SYNC PULSE
VSYNC_COMP
SYNC_LPF_RESET
SYNC OFF
SYNC_PULSE_PD
RESPONSE
tA_SYNC_DLY tPD_DLY tPD_ON tSYNC_LPF_RST_ST tTRIG tSYNC_LPF_RST tSYNC_OFF_xxx tTIMESLOTx
Figure 28. Synchronization Pulse Detection Timing
4.2.1.2
Synchronization Pulse Pull-down Function
The device includes an optional Sync pulse pull-down function for systems in which the master device does not include an active pull-down function. The modulation current pull-down circuit is used, which sinks IMOD-IIDLE additional current from the IDATA pin. The pull-down current is activated after tPD_DLY (referenced to tTRIG), and is activated for tPD_ON.
4.3
4.3.1
Data Transmission Data Link Layer
Bit Encoding
The device outputs data by modulation of the VCC current using Manchester 2 Encoding. Data is stored in a transition occurring in the middle of the bit time. The signal idles at the normal quiescent supply current. A logic low is defined as an increase in current at the middle of a bit time. A logic high is defined as a decrease in current at the middle of a bit time. There is always a transition in the middle of the bit time. If consecutive "1" or "0" data are transmitted, There will also be a transition at the start of a bit time.
IMOD CURRENT IDLE CURRENT CONSECUTIVE `0' DATA BITS CONSECUTIVE `1' DATA BITS
`0' BIT
`1' BIT
SENSED HIGH SENSED LOW
tBIT
Figure 29. Manchester 2 Data Bit Encoding
MMA52xxWR Preliminary 34 Sensors Freescale Semiconductor
4.3.2
Data Transmission
Transmission frames are composed of two start bits, an 8-Bit or 10-bit data word, and error detection bit(s). Data words are transmitted least-significant bit (LSB) first. A typical Manchester-encoded transmission frame is illustrated in Figure 30.
Data Bit
SB1
SB0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
PAR
SB1
IMOD Bit Value `0' `0' `1' `1' tBIT tTRAN = tBIT * (2+DATASIZE+(P_CRC?3:1)) tFRAME `1' `0' `0' `1' `1' `1' `1' `0' `1'
Figure 30. Example Manchester Encoded Data Transfer - PSI5-x10P
4.3.3
Error Detection
Error detection of the transmitted data is accomplished via either a parity bit, or a 3-Bit CRC. The type of error detection used is selected by the P_CRC bit in the DEVCFG register.
4.3.4
Parity Error Detection
When parity error detection is selected, even parity is employed. The number of logic `1' bits in the transmitted message must be an even number.
4.3.5
3-Bit CRC Error Detection
When CRC error detection is selected, a 3-bit CRC is appended to each response message. The 3-bit CRC uses a generator polynomial of g(x) = X3+X+1, with a seed value = `111'. Data from the transmitted message is read into the CRC calculator LSB first, and the data is augmented with three `0's. Start bits are not used in the CRC calculation.Table 7 shows some example CRC calculation values for 10-bit data transmissions. Table 7. PSI5 3-Bit CRC Calculation Examples
Data Transmitted HEX 0x000 0x0CC 0x151 0x1E0 0x1F4 0x220 0x275 0x333 0x3FF D9 0 0 0 0 0 1 1 1 1 D8 0 0 1 1 1 0 0 1 1 D7 0 1 0 1 1 0 0 0 1 D6 0 1 1 1 1 0 1 0 1 D5 0 0 0 1 1 1 1 1 1 D4 0 0 1 0 1 0 1 1 1 D3 0 1 0 0 0 0 0 0 1 D2 0 1 0 0 1 0 1 0 1 D1 0 0 0 0 0 0 0 1 1 D0 0 0 1 0 0 0 1 1 1 C2 1 0 0 0 0 1 1 0 1 CRC C1 1 1 0 1 1 0 1 0 0 C0 0 1 0 1 0 0 1 1 0
MMA52xxWR Sensors Freescale Semiconductor Preliminary 35
4.3.6
Data Range Values
Table 9 shows the details for each data range. Table 8. PSI5 Data Values
8-Bit Data Value Decimal Hex 10-Bit Data Value Decimal +511 +127 $7F * * * +502 +126 +125 $7E $7D +501 +500 +499 N/A N/A * * * +489 +124 +123 +122 $7C $7B $7A +488 +487 +486 +485 N/A N/A * * * +481 +480 * * * +3 +2 +1 0 -1 -2 -3 * * * -480 -481 * * * -496 -497 * * * -512 Hex $1FF * * * $1F6 $1F5 $1F4 $1F3 * * * $1E9 $1E8 $1E7 $1E6 $1E5 * * * $1E1 $1E0 * * * $03 $02 $01 0 $3FF $3FE $3FD * * * $220 $21F * * * $210 $20F * * * $200 Initialization Data IDs Block ID 1 - 16 (10-bit Mode) (IDx) Block ID 1 - 4 (8-Bit Mode) (IDx) Initialization Data Codes 10-Bit Status Data Nibble 1 - 16 (0000 - 1111) (Dx) 8-Bit Status Data Nibble 1 - 4 (00 - 11) (Dx) Maximum negative acceleration value Negative acceleration values 0g level Positive acceleration values Maximum positive acceleration value Reserved Sensor Busy Sensor Ready Sensor Ready, but Unlocked Reserved Sensor Defect Error Message Description
Reserved
+121 +120 * * * +3 +2 +1 0 -1 -2 -3 * * * -120 -121 * * * -124 -125 * * * -128
$79 $78 * * * $03 $02 $01 0 $FF $FE $FD * * * $88 $87 * * * $84 $83 * * * $80
MMA52xxWR Preliminary 36 Sensors Freescale Semiconductor
4.4
Initialization
Following power-up, the device proceeds through an initialization process which is divided into 3 phases: * Initialization Phase 1: No Data transmissions occur * Initialization Phase 2: Sensor self-test and transmission of configuration information * Initialization Phase 3: Transmission of "Sensor Busy", and "Sensor Ready" / "Sensor Defect" message Once initialization is completed the device begins normal mode operation, which continues as long as the supply voltage remains within the specified limits.
Sync Pulses Ignored or Program Mode Entry
Normal Mode Sync Pulses
VIDLE+ VSYNC VIDLE
...
GND IIDLE + IMOD
IIDLE
POR INIT 1 INIT 2 INIT 3 NORMAL MODE
Figure 31. PSI5 Sensor 10-Bit Initialization During PSI5 initialization, the device completes an internal initialization process consisting of the following: * Power-on Reset * Device Initialization * Program Mode Entry Verification * Offset Cancellation Initialization (2 Stages) * Self-Test Figure 32 shows the timing for internal and external initialization.
PSI5 Initialization Phase 1
tPSI5_INIT1
PSI5 Initialization Phase 2
tPSI5_INIT2
PSI5 PSI5 Initialization Normal Mode Phase 3
tPSI5_INIT3
POR Internal Delay tINT_INIT
Self-Test Offset Cancellation Offset Cancellation Raw Offset Stage 1 Stage 2 Calculation
tOC1 tOC2 tST1
Self-Test Self-Test Deflection Normal Data Verification Calculation
tST2 tST3
Self-Test Repeat (If Necessary)
ST_RPT * tST
Sync Pulses Ignored
tRS_PM
Programming Mode Entry 1) Min. 31 sync pulses 2) PME command Otherwise Sync Pulses Ignored
tPME
No PM Entry PM Entry No Transmissions In Response to Sync Pulses
tPROG_MODE_START_DELAY
Programming Mode
Figure 32. Initialization Timing MMA52xxWR Sensors Freescale Semiconductor Preliminary 37
4.4.1
PSI5 Initialization Phase 1
During PSI5 initialization phase 1, the device begins internal initialization and self checks, but transmits no data. Initialization begins with the sequence below and shown in Figure 32: * Internal Delay to ensure analog circuitry has stabilized (tINT_INIT) * Offset Cancellation phase 1 Initialization (tOC1) * Monitor for the Programming Mode Entry Sequence (tPME) - A sequence of sync pulses received during the program mode entry window in PSI5 initialization phase 1 will allow the device to enter into a PSI5 programming mode if the LOCK_U bit is not set. Reference Section 5.2 for details. * Offset Cancellation phase 2 Initialization (tOC2) * If the Programming Mode Entry Sequence is not detected, the device enters Initialization Phase 2 (tPSI5_INIT2)
4.4.2
PSI5 Initialization Phase 2
During PSI5 initialization phase 2, the device continues it's internal self checks and transmits the PSI5 initialization phase 2 data. The PSI5 initialization data transmission format varies depending on whether the device is programmed for 8-bit or 10-bit data. Initialization is transmitted using the initialization data codes and IDs specified in Table 12, and in the order shown in Figure 33 and Figure 34.
D1 ID11 D11 ID12 D12 ... ID1k D1k ID21 D21 ID22 D2 D22 ... ID2k D2k ... ... ... D32 ID321 D321 ID322 D322 ... ID32k D32k
Repeat k times
Repeat k times
Repeat k times
Figure 33. PSI5 Initialization Phase 2 Data Transmission Order (10-bit Mode)
D1 ID1H
1
D2 ... ID1H
k
... ... ID1L
k
D9 ID9L
1
D1H1
ID1H
2
D1H2
D1Hk
ID1L
1
D1L1
ID1L
2
D1L2
D1Lk
... ...
D9L1
ID9L
2
D9L2
...
ID9L
k
D9Lk
Repeat k times
Repeat k times
Repeat k times
Figure 34. PSI5 Initialization Phase 2 Data Transmission Order (8-bit Mode) The Initialization phase 2 time is calculated with the following equation:
t PHASE2 = TRANS NIBBLE x k x ( DataFields ) x t S - S
where: * TRANSNIBBLE = # of Transmissions per Data Nibble 2 for 10-bit Data: 1 for ID, and 1 for Data 4 for 8-bit Data: 2 for ID, and 2 for Data = the repetition rate for the data fields = 32 data fields for 10-bit data, 9 data fields for 8-bit data = Sync Pulse Period
*k * Data Fields * tS-S
MMA52xxWR Preliminary 38 Sensors Freescale Semiconductor
4.4.2.1
PSI5 Initialization Phase 2 (10-Bit Mode)
In PSI5 initialization phase 2, 10-bit mode, the device transmits a sequence of sensor specific configuration and serial number information. The transmission data is in conformance with the PSI5 specification, Revision 1.3 and AKLV27, Revision 1.10. The data content and transmission format is shown in Table 9 and Table 10. Table 9 shows the 10-bit phase 2 timing for different operating modes. Times are calculated using the equation in Section 4.4.2. Table 9. Initialization Phase 2 Time (10-Bit Mode)
Operating Mode Asynchronous Mode (228 s) Synchronous Mode (500 s) Repetition Rate (k) 8 4 # of Transmissions 512 256 Nominal Phase 2 Time 116.7 ms 128.0 ms
Table 10. PSI5 Initialization Phase 2 Data (10-Bit Mode)
PSI5 V1.2 PSI5 V1.2 Field ID # Nibble ID # F1 F2 F3 F4 D1 D2, D3 D4, D5 D6, D7 Page Address PSI5 Nibble Address 0000 0001, 0010 0011, 0100 0101, 0110 Register Address Hard-coded Hard-coded Hard-coded Hard-coded U_DIR[1:0] = 00: 0000 U_DIR[1:0] = 01: 0100 U_DIR[1:0] = 10: 1000 U_DIR[1:0] = 11: 1100 (not used) 60g: 0111 120g: 1000 240g: 1001 480g: 1010 DEVCFG2[7:4] DEVCFG2[3:0] Hard-coded Hard-coded DEVCFG6[3:0] DEVCFG7[7:0], DEVCFG8[4:0] converted to Binary coded Julian Date Reference Section 3.1.5.5 SN0 (High Nibble) SN0 (Low Nibble) SN1 (High Nibble) SN1 (Low Nibble) SN2 (High Nibble) SN2 (Low Nibble) SN3 (High Nibble) SN3 (Low Nibble) Initial Raw Offset (Offset[3:0]) Initial Raw Offset (Offset7:4]) ([AvgSelfTest[1:0],Offset[9:8]]) Average Self-Test (AvgSelfTest[5:2]) Average Self-Test (AvgSelfTest[9:6]) DEVCFG1 [7:4] Description Protocol Revision = V1.3 Number of Data Blocks = 32 Manufacturer = Freescale Sensor Type = Acceleration (high g) Value 0100 0010 0000 0100 0110 0000 0001
D8 F5 D9 0
0111
Axis
User
1000
Range
Varies
F6
D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 1
1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Sensor Specific Information Sensor Specific Information Product Revision Product Revision Product Revision Production Date Information Production Date Information Production Date Information Production Date Information Opuntia Serial Number Opuntia Serial Number Opuntia Serial Number Opuntia Serial Number Opuntia Serial Number Opuntia Serial Number Opuntia Serial Number Opuntia Serial Number Raw Offset1 (If INIT2_EXT=1, `0000' otherwise) Raw Offset1 (If INIT2_EXT=1, `0000' otherwise) Raw Off/Avg (If INIT2_EXT=1, `0000' otherwise) Avg (If INIT2_EXT=1, `0000' otherwise) Avg Self-Test1 (If INIT2_EXT=1, `0000' otherwise) Sensor Specific (If INIT2_EXT=1, `0000' otherwise) Self-Test1 ST1
User User 0001 0001 User User User User User Factory Factory Factory Factory Factory Factory Factory Factory Varies Varies Varies Varies Varies Varies
F7
F8
F9
D27 D28 D29 D30 D31 D32
1.
Offset and average self-test data will only be transmitted with sync pulse periods that guarantee the self-test phase1 & phase 2 will be complete prior to required transmission. If sync pulse periods faster than this are used, `0's will be transmitted instead of offset and/or average self-test data.
MMA52xxWR Sensors Freescale Semiconductor Preliminary 39
4.4.2.2
Initialization Phase 2 (8-Bit Mode)
In PSI5 initialization phase 2, 8-bit mode, the device transmits a sequence of sensor specific configuration and serial number information. The transmission data uses a format similar to the PSI5 specification, Revision 1.3 10-Bit format modified for 8-bit transmission. The data content and transmission format is shown in Table 11 and Table 12. Table 11 shows the 8-bit phase 2 timing for different operating modes. Times are calculated using the equation in Section 4.4.2.
Table 11. Initialization Phase 2 Time (8-Bit Mode)
Operating Mode Asynchronous Mode 0 (228 s) Synchronous Mode (500 s) Repetition Rate (k) 16 8 # of Transmissions 576 288 Nominal Phase 2 Time 131.3 ms 144.0 ms
Table 12. PSI5 Initialization Phase 2 Data (8-Bit Mode)
PSI5 V1.2 PSI5 V1.2 Page Field ID # Nibble ID # Address F1 F1 F2 F2 F2 F2 F3 F3 F3 F3 F4 F4 F4 F4 F5 F5 F5 F5 D1 H D1 L D2 H D2 L D3 H D3 L D4 H D4 L D5 H D5 L D6 H D6 L D7 H D7 L D8 H D8 L D9 H D9 L 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 PSI5 Half-Nibble Address 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 Register Address Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded Hard-coded U_DIR[1:0] = 00: 0000 U_DIR[1:0] = 01: 0100 U_DIR[1:0] = 10: 1000 U_DIR[1:0] = 11: 1100 (not used) 60g: 0111 120g: 1000 240g: 1001 480g: 1010 Description Protocol Revision = V1.3 Protocol Revision = V1.3 Number of Data Blocks = 9 Number of Data Blocks = 9 Number of Data Blocks = 9 Number of Data Blocks = 9 Satellite Manufacturer = Freescale Satellite Manufacturer = Freescale Satellite Manufacturer = Freescale Satellite Manufacturer = Freescale Sensor Type = Acceleration (high g) Sensor Type = Acceleration (high g) Sensor Type = Acceleration (high g) Sensor Type = Acceleration (high g) Value 01 00 00 10 00 00 01 00 01 10 00 00 00 01 User Axis User Varies Range Varies
MMA52xxWR Preliminary 40 Sensors Freescale Semiconductor
4.4.3
Internal Self-Test
During PSI5 Initialization Phase 2 and Phase 3, the device completes it's internal self-test as described below and shown in Figure 32. * Self-Test Phase 1 - Raw Offset Calculation - The average offset is calculated for tST1 (Self-Test Disabled). - If the INIT2_EXT bit is set, this 10-bit value is transmitted in Initialization Phase 2 (reference Section 4.4.2). * Self-Test Phase 2 - Self-Test Deflection Verification - The offset cancellation value is frozen for tST2 + 2ms - Self-Test is enabled - After tST2/2, the acceleration output value is averaged for tST2/2 to determine the self-test value - If the INIT2_EXT bit is set, this10-bit value is transmitted in Initialization Phase 2 (reference Section 4.4.2). - The self-test value is compared against the limits specified in Section 2.5 - Self-Test is disabled * Self-Test Phase 3 - Self-Test Normal Data Calculation - The average offset is calculated for tST3 - If Self-Test passed, the device advances to normal mode - If Self-Test failed, the device repeats Self-Test Phases 1 through 3 up to ST_RPT times.
4.4.4
Initialization Phase 3
During PSI5 initialization phase 3, the device completes it's internal self checks, and transmits a combination of "Sensor Busy", "Sensor Ready", or "Sensor Defect" messages as defined in Table 8. The number of messages transmitted in initialization phase 3 varies depending on the mode of operation, and the number of self-test repetitions. Self-Test is repeated on failure up to ST_RPT times to provide immunity to misuse inputs during initialization. Self-Test terminates successfully after one successful self-test sequence. Table 13 shows the nominal Initialization Phase 3 times for different operating modes and self-test repeats. Times are calculated using the following equation.
PSI5INIT3
( t INTINIT + t OC1 + t OC2 + ( t ST1 + t ST2 + t ST3 ) x ( STRPT + 1 ) ) - ( t PSI5INIT1 + t PSI5INIT2xx ) = ROUNDUP -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2 x t S - S tS - S
MMA52xxWR Sensors Freescale Semiconductor Preliminary 41
Table 13. Initialization Phase 3 Time
Operating Mode Self-Test Repetitions 0 1 8-Bit Asynchronous Mode 0 (228 s) 2 3 4 5 0 1 10-Bit Asynchronous Mode 0 (228 s) 2 3 4 5 0 1 8-Bit Synchronous Mode (500 s) 2 3 4 5 0 1 10-Bit Synchronous Mode (500 s) 2 3 4 5 # of Sensor Busy Messages 0 359 780 1201 1622 2043 2 423 844 1265 1686 2107 2 0 138 330 522 714 906 0 170 362 554 746 938 1.00 74.00 170.00 266.00 362.00 458.00 1.00 90.00 186.00 282.00 378.00 474.00 # of Sensor Ready or Sensor Defect Messages Nominal Phase 3 Time (ms) 0.46 86.18 182.17 278.16 374.15 470.14 4.79 100.78 196.76 292.75 388.74 484.73
MMA52xxWR Preliminary 42 Sensors Freescale Semiconductor
4.5
4.5.1
4.5.1.1
PSI5 Transmission Modes
Normal Mode
Asynchronous Mode
The device can be programmed to respond in asynchronous mode with the following settings: * TRANS_MD[1:0] = `00' ("Normal Mode") * ASYNC = `1' in the DEVCFG6 Register * TIMESLOTA[9:0] = 0x000 in the DEVCFG3 and DEVCFG4 registers In asynchronous mode, the device transmits data at a fixed rate (tASYNC) and will not respond to normal sync pulses. However, during initialization phase 1, sync pulses are monitored to decode the Programming Mode Entry Command and allow entry into Programming Mode if the LOCK_U bit is not set.
4.5.1.2
Simultaneous Sampling Mode
The device can be programmed to respond in Simultaneous Sampling Mode by setting the TRANS_MD[1:0] bits to "Normal Mode", and by programming the LATENCY bit to "Simultaneous Sampling Mode". In Simultaneous Sampling Mode, the most recent interpolated acceleration data sample is latched at tTRIG (rising edge of Sync Pulse) and transmitted starting at the time programmed in TIMESLOTA[9:0], relative to tTRIG.
tLAT_INTERP tTIMESLOTA
Figure 35. Simultaneous Sampling Mode
MMA52xxWR Sensors Freescale Semiconductor Preliminary 43
4.5.1.3
Synchronous Sampling Mode with Minimum Latency
The device can be programmed to respond in Synchronous Sampling Mode with minimum latency by setting the TRANS_MD[1:0] bits to "Normal Mode", and by programming the LATENCY bit to "Synchronous Sampling Mode". In Synchronous Sampling Mode, the most recent interpolated acceleration data sample is latched at the time programmed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync Pulse). The data is transmitted starting at the time programmed in TIMESLOTA[9:0], relative to tTRIG.
tLAT_INTERP + tDATASETUP_synch tTIMESLOTA
Figure 36. Synchronous Sampling Mode with Minimum Latency
MMA52xxWR Preliminary 44 Sensors Freescale Semiconductor
4.5.2
Synchronous Double Sample Rate Mode
The device can be programmed to respond in Synchronous Double Sample Rate Mode with minimum latency by setting the TRANS_MD[1:0] bits to "Synchronous Double Sample Rate Mode". The LATENCY bit does not affect operation in this mode. In Synchronous Double Sample Rate Mode, the most recent interpolated acceleration data sample is latched at the time programmed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync Pulse). This data is transmitted starting at the time programmed in TIMESLOTA[9:0], relative to tTRIG. In addition, the most recent interpolated acceleration data sample is latched at the time programmed in TIMESLOTB[9:0], relative to tTRIG (rising edge of Sync Pulse) This data is transmitted starting at the time programmed in TIMESLOTB[9:0], relative to tTRIG. When Synchronous Double Sample Rate Mode is enabled, PSI5 Initialization data is transmitted in both TIMESLOTA[9:0] and TIMESLOTB[9:0]. Identical data is transmitted in both Time slots, including the 10-bit resolution Raw Offset and Self-Test Data in Field 9, D27 though D31 if enabled.
tLAT_INTERP+tDATASETUP_double tLAT_INTERP+tDATASETUP_double
tTIMESLOTA tTIMESLOTB
Figure 37. Synchronous Double Sample Rate Mode Note: In the event that the programmed values in TIMESLOTA[9:0] and TIMESLOTB[9:0] result in a conflict, no data will be transmitted in TIMESLOTB[9:0].
MMA52xxWR Sensors Freescale Semiconductor Preliminary 45
4.5.3
16-Bit Resolution Mode
The device can be programmed to respond in 16-bit Resolution Mode by setting the TRANS_MD[1:0] bits to "16-bit Resolution Mode". In this mode, the 26 bit digital output from the DSP is clipped and scaled to a 16-bit word. Figure 38 shows the method used to establish the 16-bit data word from the 26 bit DSP output.
Over Range
Signal
Noise D8 D7 D6
Margin D5 ... D2 D1 D0
D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
16-bit Data Word
D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
Using Rounding
Figure 38. 16-Bit Output Scaling Diagram 16-Bit Resolution Mode can be programmed to operate in either "Simultaneous Sampling Mode", or "Synchronous Sampling Mode", by setting the LATENCY bit to the desired operating mode. In Simultaneous Sampling Mode, the most recent interpolated acceleration data sample is latched at tTRIG (rising edge of Sync Pulse). In Synchronous Sampling Mode, the most recent interpolated acceleration data sample is latched at the time programmed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync Pulse). The most significant 10 bits (D[21:12]) are truncated and transmitted starting at the time programmed in TIMESLOTA[9:0], relative to tTRIG. The 16-bit value is then clipped to 480 counts, and the least significant 10 bits (D15:D6) are transmitted starting at the time programmed in TIMESLOTB[9:0], relative to tTRIG. When 16-Bit Resolution Mode is enabled, PSI5 Initialization data is transmitted in both TIMESLOTA[9:0] and TIMESLOTB[9:0]. Identical data is transmitted in both Time slots, including the 10-Bit Resolution Raw Offset and Self-Test Data in Field 9, D27 though D31 if enabled.
tTIMESLOTA tTIMESLOTB
tLAT_INTERP + tDATASETUP_16
Figure 39. 16-Bit Resolution Mode with Synchronous Sampling Note: In the event that the programmed values in TIMESLOTA[9:0] and TIMESLOTB[9:0] result in a conflict, no data will be transmitted in TIMESLOTB[9:0].
MMA52xxWR Preliminary 46 Sensors Freescale Semiconductor
4.5.4
Daisy Chain Mode
The device can be programmed to operate in Daisy Chain Mode by setting the TRANS_MD[1:0] bits to "Daisy Chain Mode". Daisy Chain Mode can be programmed to operate in either "Simultaneous Sampling Mode", or "Synchronous Sampling Mode" by setting the LATENCY bit to the desired operating mode. In Simultaneous Sampling Mode, the most recent interpolated acceleration data sample is latched at tTRIG (rising edge of Sync Pulse). In Synchronous Sampling Mode, the most recent interpolated acceleration data sample is latched at the time programmed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync Pulse). When programmed to operate in Daisy Chain Mode, the procedure below is followed: * On power-up, the device proceeds through normal PSI5 initialization as specified in Section 4.4 using a predefined time slot tTIMESLOT_DCP. * Upon successful completion of Initialization Phase 3, including the 2 "Sensor Ready" or Sensor Defect" messages, responses to sync. pulses are terminated and the device waits for a PSI5 "Set Address" command defined in Table 14 and Table 15. - The Daisy Chain Programming command and response formats are defined in Section 5.4. - Valid Daisy Chain Addresses are defined in Table 16. - The response to the PSI5 Set Address command uses the pre-defined time slot tTIMESLOT_DCP. * After receiving a valid address and completing the response, sync. pulses are blanked for tDC_BLANKING. Once the blanking time expires, the device does not respond to any sync. pulses until a "Run Mode" command is received, as defined in Table 14 and Table 15. * When the "Run Mode" command is received, the device responds to this command using the programmed daisy chain time slot. All commands are then ignored, and sync pulses are responded to with acceleration data using the following response format, regardless of the state of the relevant bits in the Device Configuration Registers:
Parameter Time Slot Data Size Error Checking Baud Rate Reference Section 3.1.4.3 Section 3.1.3.5 Section 3.1.3.7 Section 3.1.3.8 Value Default time slot specified in Table 16 10-bit data Even Parity Low Baud Rate: 125 kBaud
* During initialization and Run Mode, the Sync pulse pull-down is enabled as specified in Section 3.1.3.3. Table 14. Daisy Chain Programming Commands and Responses
# D0 D1 CMD Type Short Short SAdr A2 0 1 A1 0 1 A0 0 1 F2 A2 0 FC F1 A1 0 F0 A0 0 Command Set Sensor Address (Daisy Chain) Broadcast Message - "Run Mode" Response (OK) RC OK OK RD1 SAdr 0x000 Response (Error) RC Error Error RD1 ErrN ErrN
Table 15. Daisy Chain Programming Response Code Definitions
Response Code RC = OK RC = Error SAdr Definition Command Message Received Properly Error during transmission of Command Message Programmed Sensor Address, prepended with 0s Value 0x1E1 0x1E2 Varies
Table 16. Valid Daisy Chain Addresses
Sensor Address (SAdr) A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Address of un-programmed sensor Sensor Address 1 Sensor Address 2 Sensor Address 3 Sensor Address 4 Sensor Address 5 Sensor Address 6 Global Address for Broadcast Message to all Sensors N/A CLOSED CLOSED CLOSED OPEN OPEN OPEN N/A N/A tTIMESLOT_DC1 tTIMESLOT_DC2 tTIMESLOT_DC3 tTIMESLOT_DC1 tTIMESLOT_DC2 tTIMESLOT_DC3 N/A Description Bus Switch Control Default Time Slot
MMA52xxWR Sensors Freescale Semiconductor Preliminary 47
4.6
4.6.1
Error Handling
Sensor Defect Message
The following failures will cause the device to transmit a "Sensor Defect" error message:
Error Condition Offset Error Self-Test Failure IDEN_B, IDEF_B flag cleared Error Type Temporary (Normal transmissions continue once offset returns within limits) Latched until reset Latched until reset
4.6.2
No Response Error
The following failures will cause the device to stop transmitting:
Error Condition Undervoltage Failure (VCC) Under- / Over-Temperature Failure Error Type Temporary: Normal transmissions continue once voltage returns above failure limit) Temporary: Normal transmissions continue once temperature returns within the specified limits)
MMA52xxWR Preliminary 48 Sensors Freescale Semiconductor
5
5.1
PROGRAMMING MODE VIA PSI5
Introduction
Programming mode via PSI5 is a synchronous communication mode that allows for bidirectional communication with the device. Programming mode is intended for factory programming of the OTP array. It is not intended for use in normal operation.
5.2
Programming Mode Via PSI5 Entry
* The device is unlocked (the LOCK_U bit in the DEVCFG2 register is `0'). * At least 31 sync pulses are detected, directly preceding the Programming Mode Entry Short Command during the Programming Mode Entry Window shown in Figure 32. - The window timing is defined in Section 2.6 (tPME). - The Sync pulses and Programming Mode Entry command must be received with a sync pulse period of tS-S_PM_L
The device enters programming mode if and only if the following sequence occurs:
If the Programming Mode entry requirement is not met: * Programming Mode Entry is blocked until the device is Reset. * The device proceeds with PSI5 Initialization Phase 2, and PSI5 Initialization Phase 3. * The device enters normal mode, and responds as programmed to normal sync pulses. If the Programming Mode entry requirement is met: * Normal transmissions to sync pulses are terminated. * After a pre-defined Start Delay, the device begins to decode PSI5 Short and Long Commands. * The device responds only to valid PSI5 Short and Long Commands addressed to Sensor Address `001', as defined in Table 18. Note: The sync pulse pull-down is disabled in the Programming Mode Entry Window regardless of the state of the SYNCPD bit.
MMA52xxWR Sensors Freescale Semiconductor Preliminary 49
5.3
5.3.1
Programming Mode Via PSI5 - Data Link Layer
Programming Mode Via PSI5 - Command Bit Encoding
Commands messages are transmitted via the modulation of the supply voltage. The presence of a sync pulse is a logic '1' and the absence of a sync pulse is a logic '0'. Sync pulses are expected at a rate of tS-S_PM_L.
5.3.2
Programming Mode Via PSI5 - Command Message Format
Command message data frames consist of a start condition, 3 Start Bits (S[2:0]), a 3 bit Sensor Address (SAdr[2:0]), a 3-bit Function Code (FC[2:0]), an optional Register Address (RAdr[5:0]), an optional data field (D[3:0]), and a 3-bit CRC (C[2:0]. The start condition consists of one of the following: 1. A minimum of 5 consecutive logic `0's (with not sync bits) 2. A minimum of 31 consecutive logic `1's The command message format is shown in Figure 41.
Start Bits S2 0 S1 1 S0 0 Sensor Address SA0 0 SA1 0 SA2 1 Function Code FC0 0 FC1 1 FC2 0 RA0 0 Register Address RA1 0 RA2 0 RA3 0 RA4 0 RA5 0 D0 1 Data D1 1 D2 1 D3 1 C2 0 CRC C1 0 CRC Data to be written to register (optional) Register Address (optional) Function Codes for MMA52xxWR (Reference Section 5.3.6) Sensor Address - Fixed at 001 for Opuntia Start Bit Sequence = 010 C0 0 RC Response RD1 RD0
$3FF $3FF $3FF
Figure 40. Programming Mode Via PSI5 Command Data Format Bit stuffing is necessary to maintain a synchronized time base between the command master and the device. A logic `1' Sync bit is added every 4th bit in the command message to ensure there will never be more than 3 logic '0' bits in a row.
Start Bits Sensor Address Function Code Register Address Data CRC RC $1E2 Response RD1 $3FF RD0 $3FF
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy D0 D1 D2 Sy D3 C2 C1 Sy C0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0
Figure 41. Programming Mode Via PSI5 Command Data Format with Sync Bits Once a command is received and verified, the device expects 2 to 3 consecutive sync pulses (depending upon the command message lengths described below). For each of these sync pulses, the device will respond with the following settings:
Parameter Time Slot Data Size Error Checking Baud Rate Sync Pulse Pull-down Register Bits N/A DATASIZE = 0 P_CRC = 0 BAUD SYNCPD Reference N/A Section 3.1.3.5 Section 3.1.3.7 Section 3.1.3.8 Section 3.1.3.3 Value tTIMESLOT_DC1 10-bit data Even Parity 125 kBaud Disabled
Figure 42. Programming Mode Via PSI5 Response Message Settings
MMA52xxWR Preliminary 50 Sensors Freescale Semiconductor
5.3.2.1
Short Frame Command and Response Format
Short frames are the simplest type of command message. No data is transmitted in a short frame command. Only specific instructions are performed in response to short frame commands. The Short Frame format is shown in Figure 43. Short Frame commands and responses are defined in Section 5.3.6, Table 18.
Start Bits S2 0 S1 1 S0 0 Sy 1 Sensor Address SA0 SA1 SA2 Sy 1 0 0 1 Function Code FC0 FC1 FC2 Sy 0 0 1 1 C2 0 CRC C1 0 C0 0 Response RC $1E2 RD1 $3FF
Figure 43. Programming Mode Via PSI5 Short Command and Response Format
5.3.2.2
Long Frame Command and Response Format
Long frames allow for the transmission of data nibbles for register writes. The device can provide register data in response to a read or write request. The Long Frame format is shown in Figure 44. Long Frame commands and responses are defined in Section 5.3.6.
Start Bits Sensor Address Function Code Register Address Data CRC RC $1E2 Response RD1 $3FF RD0 $3FF
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy D0 D1 D2 Sy D3 C2 C1 Sy C0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0
Figure 44. Programming Mode Via PSI5 Long Command and Response Format
5.3.3
Command Message CRC
Programming mode command error checking is accomplished by a 3-bit CRC. The 3-bit CRC is calculated using all message bits except start bits and sync bits. The CRC verification uses a generator polynomial of g(x) = X3+X+1, with a seed value = `111'. The data is provided to the CRC calculator in the order received (LSB first, SAdr, FC, RAdr, Data), and then augmented with three `0's. Table 8 shows some example CRC calculation values for 10-bit data transmissions. The calculated CRC is then compared against the received 3-bit CRC (received MSB first). If a CRC mismatch is detected, the device responds with a CRC Error response as defined in Section 5.3.7.
5.3.4
Command Sync Pulse Blanking Time
In Programming Mode and Programming Mode Entry, the device employs a fixed Sync Pulse blanking time of tSYNC_OFF_500 regardless of the state of the BLANKTIME bit.
5.3.5
Command Timeout
In the event that the device does not detect a sync pulse within a 4-bit window time (missing sync bit), the command reception will be terminated and the device will respond to the next sync pulse with a Short Frame Framing Error response as defined in Section 5.3.7.
MMA52xxWR Sensors Freescale Semiconductor Preliminary 51
5.3.6
Programming Mode Via PSI5 Command and Response Summary
Table 17. Programming Mode Via PSI5 Commands and Responses
# CMD Type SAdr FC Command Register Address Data Field Response (OK) RC RD1 RD0 RC Response (Error) RD1 RD0
S0 S1 S2 S3 LR LW
Short Short Short Short 001 Long Long
100 101 110 111 010 011 000 001
Execute Programming of NVM Invalid Command Invalid Command Enter Programming Mode Read nibble located at address RA5:RA0 Write nibble to register RA5:RA0 Invalid Command Invalid Command
N/A N/A N/A N/A Varies Varies Any Any
N/A N/A N/A N/A Varies Varies Any Any
OK
0x2AA No Response No Response
N/A
Error
ErrN No Response No Response
N/A
OK OK OK
0x0CA RData WData
N/A RData+1 Error
No Response ErrN ErrN 0x000 0x000
RA5:RA0 Error
XLR XLong XLW XLong
No Response No Response
No Response No Response
Note: When reading the last address in the data array, RData+1 will always return 0x00. Table 18. Programming Mode Via PSI5 Response Code Definitions
Response Code RC = OK RC = Error RData RData + 1 WData Definition Command Message Received Properly Error during transmission of Command Message Byte Contents of Register located at Byte address in which nibble address RA5:RA0 falls in. (Example: For RA5:RA0 = $04 - RData = Data at Byte Address $02) Byte Contents of Register located at Byte address in which nibble address RA5:RA0 +2 falls in. (Example: For RA5:RA0 = $04 - RData + 1= Data at Byte Address $03) Byte Contents of Register located at Byte address in which nibble address RA5:RA0 falls in after write operation. (Example: For RA5:RA0 = $04 - RData = Data at Byte Address $02) Value 0x1E1 0x1E2 Varies Varies Varies
5.3.7
Programming Mode Via PSI5 Error Response Summary
Table 19. Error Response Summary
ErrN* 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Reserved 1100 1101 1110 1111 * ErrN is transmitted in the 4 LSBs of RD1. All other bits in the response data field are set to `0'. Reserved No Mnemonic General Framing CRC Address FC Data Range Write Protect Reserved Description General Error Framing Error CRC Error on Received Message Sensor Address Not Supported Function Code Not Supported Unsupported Register Address Destination Address is Write protected (Locked) Reserved Supported By MMA52xx No Yes Yes No (Invalid Address is ignored) No (N/A) Yes Yes No
MMA52xxWR Preliminary 52 Sensors Freescale Semiconductor
5.4
OTP Programming Via PSI5 Procedure
1. Enter Programming Mode. 2. Load desired data into the OTP shadow registers using PSI5 Long Write commands. 3. Send "Execute Programming of NVM "Short command. 4. Set VCC = VPP prior to, or within tPROG_HOLD after the "Execute Programming of NVM" Command has been transmitted. There is an internal delay of tPROG_DELAY after the "Execute Programming of NV" Command is received until the OTP programming begins. a. b. OTP write time depends on the number of bits being written to `1'. Each bit that is programmed requires tPROG_BIT. During the OTP Write sequence, sync pulses will be ignored. However, transmission of sync pulses during the OTP Write sequence should be prevented.
5. Read the SC register and verify IDEF_B flag is set (indicating the write is complete and successful, and the shadow registers have been refreshed with the OTP contents). 6. Read the OTP register values and compare to the desired values.
MMA52xxWR Sensors Freescale Semiconductor Preliminary 53
6
SPI DIAGNOSTIC AND PROGRAMMING MODE
SPI Diagnostic and Programming Mode allows for the following functions: * * Programming of the OTP array Reading of memory registers
SPI transfers follow CPOL = 0, CPHA = 0, MSB first convention. Figure 7 shows the SPI transfer timing, and Figure 45 shows the SPI transfer protocol.
BIT SCLK CS DIN DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15 D15
D14 D14
D13 D13
D12 D12
D11 D11
D10 D10
D9 D9
D8 D8
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
Figure 45. SPI Transfer Protocol The following operations are supported in DPM: * Register pointer write * Register pointer read * Register data write * Register data read * Acceleration data read
6.0.1 6.0.2
Communication Error Detection Data Input Parity Detection
All commands except for the DPM Entry command employ odd parity to ensure data integrity. For Read commands, the parity bit is located in bit D10, and the parity is calculated using bits D15 through D11. For Write commands, the parity bit is located in bit D9, and the parity is calculated using bits D15 through D0. If a parity error is detected, both the current and subsequent commands are ignored, and the parity fault response is transmitted during the subsequent SPI transfer.
6.0.3
Data Output Parity
All responses except for the DPM entry response employ odd parity to ensure data integrity. Parity is calculated using the entire 16-bit message.
MMA52xxWR Preliminary 54 Sensors Freescale Semiconductor
6.1
DPM Entry
DPM can be activated at any time during the operation of the device, provided the SPI DPM Entry command is the first command transmitted. If an incorrect DPM Entry command is received, DPM is locked out, and cannot be activated until the device is reset. The device responds to the DPM Entry command with the logical complement of the received data as confirmation that it has been received correctly. Upon completion of a successful transfer DPM is activated. Once activated, the device will remain in DPM until a reset condition occurs. Following successful transmission of the DPM Entry command, DPM operations may be completed in any order.
6.2
DPM Command/Response Summary
Table 20 provides a summary of SPI commands and responses. Table 20. SPI Command/Response Summary
Bit Command Pin D15 D14 D13 D12 D11 D10 DIN DOUT 1 0 0 1 1 0 0 1 0 1 0 1 D9 1 0 D8 1 0 D7 0 1 D6 1 0 D5 0 1 D4 1 0 D3 1 0 D2 1 0 D1 0 1 D0 0 1
SPI DPM Entry
Register Pointer Write
DIN DOUT
0 1
1 0
0 1
0 1
1 0
1 P
P 0
X 1
A7 0
A6 0
A5 0
A4 0
A3 0
A2 0
A1 0
A0 0
Register Pointer Read
DIN DOUT
0 1
1 0
0 1
0 1
0 0
P=0 P
0 0
X 1
X A7
X A6
X A5
X A4
X A3
X A2
X A1
X A0
Register Data Write
DIN DOUT
0 1
1 0
0 1
1 0
1 0
0 P
P 1
X 0
D7 A7
D6 A6
D5 A5
D4 A4
D3 A3
D2 A2
D1 A1
D0 A0
Register Data Read
DIN DOUT
0 1
1 0
0 1
1 0
0 0
P=1 P
0 1
X 0
X D7
X D6
X D5
X D4
X D3
X D2
X D1
X D0
Acceleration Data Read
DIN DOUT
0 1
1 0
1 0
0 1
0 1
P=1 P
0 D9
0 D8
0 D7
0 D6
0 D5
0 D4
0 D3
0 D2
0 D1
0 D0
DIN DOUT
0 1
0
D[1 3]
D[1 2]
D[1 1]
D[1 D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0]
No Response (all 0s) - DPM Entry Locked Out
DIN DOUT Invalid Command Response (Waiting for SPI DPM Entry) DIN DOUT
0 1
1
1
D[1 2]
D[1 1]
D[1 D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0]
No Response (all 0s) - DPM Entry Locked Out
1 0
1 0
D[1 3]
D[1 2]
D[1 1]
D[1 D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0] No Response (all 0s) - DPM Entry Locked Out
DIN DOUT
1 0
0 1
D[1 3] D[1 3]
D[1 2] D[1 2]
D[1 1] D[1 1]
... ...
D[x] D[x]
Not SPI DPM Entry Command No Response (all 0s) - DPM Entry Locked Out
MMA52xxWR Sensors Freescale Semiconductor Preliminary 55
Table 20. SPI Command/Response Summary
Bit Command Pin D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIN Invalid Command Response DOUT
X d[1 5]
X d[1 4]
X d[1 3]
X d[1 2]
X d[1 1]
X d[1 0]
X
X
X
X
X
X
X
X
X
X
d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]
Parity Fault Response (Subsequent Message Response)
DIN DOUT
X 1
X 0
X 0
X 0
X 0
X 0
X 1
X 1
X 1
X 1
X 1
X 1
X 1
X 1
X 1
X 1
6.3
Register Pointer Operations
Access to internal registers is accomplished via a pointer register. The pointer contains the address of the register affected by register data write and read operations. Two register pointer operations are provided: Register Pointer Write, and Register Pointer Read. Command and response information is shown in Table 20.
6.4
Register Data Operations
Two register operations are provided: Register Write, and Register Read. In each case, the address of the affected register is contained in the register pointer.
6.4.1
Register Write Command
The Register Write command format is shown in Table 20. The least significant 8 bits of the Register Write command message contain the data to be written to the register pointed to by the register pointer. The least significant 8 bits of the Register Write response message contain the address of the register that was modified. The write to the register is executed during the clock cycle immediately after CS is de-asserted.
6.4.2
Register Read Command
The Register Read command format is shown in Table 20. The least significant 8 bits of the Register Read command message are ignored. The least significant 8 bits of the Register Read response message contain the contents of the register pointed to by the register pointer. 16-bit register reads are possible using consecutive Register Read commands. The high byte of a 16-bit register will automatically be frozen on a read of the low byte of the register.
MMA52xxWR Preliminary 56 Sensors Freescale Semiconductor
6.4.3
Acceleration Data Read Operations
The Acceleration Data Read command format is shown in Table 20. The response to this command provides either 8-bit, or 10-bit acceleration data depending on the state of the DATASIZE bit in the DEVCFG2 register.
Bit DATASIZE D15 D14 D13 D12 D11 D10 DATASIZE = 0 (8-Bit Data) DATASIZE = 1 (10-Bit Data) 1 1 0 0 0 0 1 1 1 1 P P D9 0 D9 D8 0 D8 D7 D7 D7 D6 D6 D6 D5 D5 D5 D4 D4 D4 D3 D3 D3 D2 D2 D2 D1 D1 D1 D0 D0 D0
6.4.4
6.4.4.1 6.4.4.2
Error Responses
Response to Invalid Commands Parity Fault Response
Reference Table 20 for responses to Invalid Commands.
If the device detects a Command Parity fault, the current, and subsequent SPI commands are ignored and the device responds to the subsequent message with the Parity Fault response, as shown in Table 20.
6.4.5
SPI OTP Programming Procedure
1. Set VCC = VPP. 2. Enter SPI DPM. 3. Load desired data into the OTP shadow registers using SPI Write commands. 4. Write 0x05 to register $44 to initiate the NVM programming. a. OTP write time depends on the number of bits being written to `1'. Each bit that is programmed requires tPROG_BIT.
5. Read the SC register and verify IDEF_B flag is set (indicating the write is complete and successful). 6. Reset the device. 7. Re-entering SPI DPM. 8. Read the OTP register values and compare to the desired values.
7
RECOMMENDED FOOTPRINT
Reference Freescale Application Note AN3111, latest revision: http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf
MMA52xxWR Sensors Freescale Semiconductor Preliminary 57
PACKAGE DIMENSIONS
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CASE 2086-01 ISSUE A 16 LEAD QFN
MMA52xxWR Preliminary 58 Sensors Freescale Semiconductor
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 2086-01 ISSUE A 16 LEAD QFN
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PACKAGE DIMENSIONS
PAGE 3 OF 3
CASE 2086-01 ISSUE A 16 LEAD QFN
MMA52xxWR Preliminary 60 Sensors Freescale Semiconductor
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MMA52xxWR2 Rev. 0 02/2010

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